Apparatus implementing instructions that impose pipeline interdependencies
US-9183611-B2 · Nov 10, 2015 · US
Intelligent caching for an operand cache
US9459869B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9459869-B2 |
| Application number | US-201313971800-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 20, 2013 |
| Priority date | Aug 20, 2013 |
| Publication date | Oct 4, 2016 |
| Grant date | Oct 4, 2016 |
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Abstract
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Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may store a subset of operands, and may use less power and have quicker access times than the register file. In some embodiments, intelligent operand prefetching may speed execution by reducing memory bank conflicts (e.g., conflicts within a register file containing multiple memory banks). An unused operand slot for another instruction (e.g., an instruction that does not require a maximum number of source operands allowed by an instruction set architecture) may be used to prefetch an operand for another instruction in one embodiment. Prefetched operands may be stored in an operand cache, and prefetching may occur based on software-provided information.
First claim
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What is claimed is: 1. An apparatus, comprising: an execution unit configured to execute instructions having up to N possible source operands, wherein N is greater than 1; a register file configured to store a plurality of operands for instructions to be executed by the execution unit; an operand cache configured to store a subset of the plurality of operands stored in the register file; and fetch circuitry configured to retrieve operands specified by instructions to be exec…
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- G06T1/20Primary
Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9459869B2 cover?
- Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may store a subset of operands, and may use less power and have quicker access times than the register file. In some…
- Who is the assignee on this patent?
- Apple Inc
- What technology area does this patent fall under?
- Primary CPC classification G06T1/20. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).