Data processing system and data processing method

Patent metadata

Field	Value
Publication number	US-9459798-B2
Application number	US-201414567656-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Oct 29, 2013
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

First claim

What is claimed is:

1. A data processing system, comprising a central processing unit (CPU), a memory, a Peripheral Component Interconnect Express (PCIe) controller, a network adapter, and at least one PCIe storage device, and further comprising:
a management unit, configured to obtain, when the data processing system receives a first data request, a first storage address of requested data in the at least one PCIe storage device according to first address information carried in the first data request,
wherein the first storage address is a memory mapping input/output (MMIO) address, wherein the network adapter directly reads data from the at least one PCIe storage device according to the first storage address, and transmits the data to a separate data processing system, or directly writes data received from the separate data processing system into the at least one PCIe storage device, wherein the separate data processing system communicates with the data processing system through a network,
wherein the CPU assigns a unique identifier to each of the at least one PCIe storage device to identify the each of the at least one PCIe storage device,
the management unit is further configured to establish a correspondence between the unique identifier and a base address in a Base Address Register (BAR) of the at least one PCIe storage device,
the management unit comprises a base address obtaining unit and a storage address obtaining unit, the base address obtaining unit is configured to obtain, when the data processing system receives the first data request of the separate data processing system that communicates with the data processing system through the network, a base address in a BAR of the requested data according to a unique identifier that is of the PCIe storage device and is carried in the first data request, and
the storage address obtaining unit is configured to obtain the first storage address of the requested data in the PCIe storage device according to the base address in the BAR and an Logical Block Address (LBA) address carried in the first data request.

2. The data processing system according to claim 1 , wherein the PCIe controller comprises an address translating unit, configured to obtain a second storage address of the data requested by the data request in the PCIe storage device according to the first storage address.

3. The data processing system according to claim 2 , wherein the second storage address is a physical address or a logical address, wherein the physical address is a linear continuous address in which data can be directly read, and the logical address is an address which is obtained after linear ordering is performed on a nonlinear continuous physical address.

4. The data processing system according to claim 2 , wherein
the address translating unit is further configured to configure a first Base Address Register (BAR) address register, wherein the first BAR address register stores a correspondence between the first storage address and the second storage address, and the second storage address is a linear continuous storage address.

5. The data processing system according to claim 2 , wherein
the address translating unit is further configured to configure a second Base Address Register (BAR) address register, wherein the second BAR address register stores a correspondence between the first storage address and a virtual address of the second storage address, the second storage address is a nonlinear continuous storage address, and the virtual address of the second storage address is obtained after linear ordering is performed on the second storage address.

6. The data processing system according to claim 1 , wherein
the first address information comprises the unique identifier and a logical block address (LBA) of the PCIe storage device.

7. The data processing system according to claim 1 , wherein
the unique identifier comprises at least one of a vender identity Vender identifier (ID), a device identity Device ID, and a hard disk serial number; or the unique identifier is an identifier which is obtained after hashing processing is performed on the at least one of the Vender ID, the Device ID, and the hard disk serial number.

8. The data processing system according to claim 1 , wherein the CPU registers the obtained first storage address in the network adapter.

9. The data processing system according to claim 1 , wherein
the data processing system further comprises a sending unit, wherein the sending unit is configured to send the first storage address obtained by the management unit to the separate data processing system.

10. The data processing system according to claim 2 , wherein the PCIe controller obtains a data request that is sent by the network adapter and carries the first storage address, and the address translating unit obtains data of the second storage address, and returns the obtained data to the network adapter, or writes the data sent by the network adapter into the second storage address.

11. The data processing system according to claim 1 , wherein the management unit further comprises a global base address obtaining unit and a global storage address obtaining unit, wherein
the global base address obtaining unit is configured to obtain, when the data processing system receives a second data request, a base address of data requested by the second data request in a BAR of the separate data processing system according to a unique identifier that is of the PCIe storage device and is carried in the second data request, wherein the second data request is a request for sending data to the separate data processing system or reading data from the separate data processing system; and
the global storage address obtaining unit is configured to obtain, according to the base address in the BAR of the separate data processing system and a Logic Block Address (LBA) address carried in the second data request, an MMIO address of the data requested by the second data request in the separate data processing system.

12. The data processing system according to claim 11 , wherein a data transform unit in a PCIe controller of the separate data processing system obtains, according to the MMIO address of the data that is requested by the second data request sent by the data processing system in the separate data processing system, a physical address or a logical address of the data requested by the second data request in the separate data processing system, wherein the physical address is a linear continuous address in which data can be directly read, and the logical address is obtained after linear ordering is performed on a nonlinear continuous physical address.

13. A data processing method, wherein the method is applied to a data processing system comprising a central processing unit (CPU), a memory, a Peripheral Component Interconnect Express (PCIe) controller, a network adapter, and at least one PCIe storage device, and the method comprises:
obtaining, by the data processing system, first address information carried in a first data request received by the data processing system;
obtaining, by the data processing system, a first storage address of requested data in the at least one PCIe storage device according to the first address information, wherein the first storage address is a memory mapping input/output (MMIO) address; directly reading, by the network adapter, data from the at least one PCIe storage device according to the first storage address, and transmitting the data to a separate data processing system, or directly writing data received from the separate data processing system into the at least one PCIe storage device, wh

Assignees

• Huawei Tech Co Ltd

Inventors

• He Jian
• Shi Guangyu
• Ni Xiaoke
• Egi Norbert
• Li Xiancai
• Liu Yu
• Liu Huawei

Classifications

• G06F13/10 Primary

  Program control for peripheral devices (G06F13/14 - G06F13/42 take precedence) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title