Device and method for generating input control signals of a serialized compressed scan circuit

Patent metadata

Field	Value
Publication number	US-9459319-B2
Application number	US-201414446342-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Jul 30, 2013
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

First claim

What is claimed is:

1. An integrated circuit device, configured to generate input control signals of a serialized compressed scan circuit, comprising:
a clock input port, configured to receive a test clock signal;
a state enable bus, configured to receive at least one state enable signal;
a control signal generating device, coupled to the state enable bus for receiving the state enable signal, coupled to the clock input port for receiving the test clock signal, and correspondingly generating a shift enable signal, a capture enable signal and a strobe signal; and
a clock gating device, coupled to the control signal generating device for receiving the shift enable signal, the capture enable signal and the strobe signal, and coupled to the clock input port for receiving the test clock signal, wherein the clock gating device, in responding to the test clock signal, generates a serialized scan clock signal when the shift enable signal is enabled and generates a scan clock signal when the strobe signal or the capture enable signal is enabled, wherein the serialized scan clock signal and the scan clock signal are part of the input control signals.

2. The integrated circuit device as claimed in claim 1 , wherein the control signal generating device comprises:
a logic operation circuit, coupled to the state enable bus for receiving an exit1-data-register state enable signal, an exit2-data-register state enable signal, a shift-data-register state enable signal, a pause-data-register state enable signal and a capture-data-register state enable signal, and correspondingly generating a first logic signal, a second logic signal and a third logic signal;
a first negative edge-triggered register, having an input terminal coupled to the logic operation circuit for receiving the first logic signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the shift enable signal;
a second negative edge-triggered register, having an input terminal coupled to the logic operation circuit for receiving the second logic signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the strobe signal; and
a third negative edge-triggered register, having an input terminal coupled to the logic operation circuit for receiving the third logic signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the capture enable signal.

3. The integrated circuit device as claimed in claim 2 , wherein the first logic signal is enabled when the exit1-data-register state enable signal, the exit2-data-register state enable signal, the shift-data-register state enable signal or the pause-data-register state enable signal is enabled,
wherein the second logic signal is enabled when the exit1-data-register state enable signal or the exit2-data-register state enable signal is enabled, and
wherein the third logic signal is enabled when the capture-data-register state enable signal is enabled.

4. The integrated circuit device as claimed in claim 3 , wherein the logic operation circuit comprises:
a first OR gate having a first input terminal coupled to the state enable bus for receiving the shift-data-register state enable signal, a second input terminal coupled to the state enable bus for receiving the pause-data-register state enable signal, and an output terminal generating the first logic signal to the input terminal of the first negative edge-triggered register;
a second OR gate having a first input terminal coupled to the state enable bus for receiving the exit1-data-register state enable signal, a second input terminal coupled to the state enable bus for receiving the exit2-data-register state enable signal, and an output terminal coupled to a third input terminal of the first OR gate and generating the second logic signal to the input terminal of the second negative edge-triggered register; and
a wire having a first terminal coupled to the state enable bus for receiving the capture-data-register state enable signal, and a second terminal outputting the capture-data-register state enable signal to serve as the third logic signal.

5. The integrated circuit device as claimed in claim 2 , wherein the logic operation circuit comprises:
a first NOR gate having an inverting input terminal coupled to the state enable bus for receiving the pause-data-register state enable signal, and a non-inverting input terminal configured to receive a test mode selection signal;
a flip-flop having an input terminal coupled to an output terminal of the first NOR gate, a positive edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal providing the third logic signal to the third negative edge-triggered register;
a second NOR gate having an inverting input terminal coupled to the state enable bus for receiving the pause-data-register state enable signal, a non-inverting input terminal coupled to the output terminal of the flip-flop, and an output terminal providing the second logic signal to the second negative edge-triggered register; and
an OR gate having a first input terminal coupled to the output terminal of the second NOR gate, a second input terminal coupled to the state enable bus for receiving the shift-data-register state enable signal, a third input terminal coupled to the state enable bus for receiving the exit1-data-register state enable signal, a fourth input terminal coupled to the state enable bus for receiving the exit2-data-register state enable signal, and an output terminal providing the first logic signal to the first negative edge-triggered register.

6. The integrated circuit device as claimed in claim 2 , wherein the first negative edge-triggered register, the second negative edge-triggered register and the third negative edge-triggered register are reset by an optional test reset signal.

7. The integrated circuit device as claimed in claim 1 , wherein the control signal generating device comprises:
a logic operation circuit, coupled to the state enable bus for receiving the at least one state enable signal, and correspondingly generating a first logic signal and a second logic signal;
a first negative edge-triggered register, having an input terminal coupled to the logic operation circuit for receiving the first logic signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the shift enable signal;
a second negative edge-triggered register, having an input terminal coupled to the logic operation circuit for receiving the second logic signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the capture enable signal; and
a negative edge-triggered counter, having an input terminal coupled to the output terminal of the first negative edge-triggered register for receiving the shift enable signal, a negative edge-triggered terminal coupled to the clock input port for receiving the test clock signal, and an output terminal coupled to the clock gating device for providing the strobe signal, wherein cyclic counting of the negative edge-triggered counter from a first value to a second value is activated when the shift enable signal is enabled and the test clock signal is at negative edge.

8. The integrated circuit device as claime

Assignees

• Ind Tech Res Inst

Inventors

• Chen Chen-An
• Chen Yee-Wen
• Wu Ming-Hsueh
• Luo Kun-Lun

Classifications

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318552 Primary

  Clock circuits details · CPC title

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title