Substrate containing low-Dk-core glass fibers having low dielectric constant (Dk) cores for use in printed circuit boards (PCBs), and method of making same

US9456496B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9456496-B2
Application numberUS-201514620880-A
CountryUS
Kind codeB2
Filing dateFeb 12, 2015
Priority dateFeb 12, 2015
Publication dateSep 27, 2016
Grant dateSep 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An enhanced substrate for use in printed circuit boards (PCBs) includes low-Dk-core glass fibers having low dielectric constant (Dk) cores. In some embodiments, the low-Dk-core glass fibers are filled with a low Dk fluid, such as a gas (e.g., air, nitrogen and/or a noble gas) or a liquid. After via holes are drilled or otherwise formed in the substrate, silane is applied to the ends of hollow glass fibers exposed in the via holes to seal the low Dk fluid within the cores of the hollow glass fibers. In some embodiments, the low-Dk-core glass fibers are filled with a solid (e.g., a low Dk resin). For example, a hollow glass fiber may be provided, and then filled with a low Dk resin in a liquid state. The low Dk resin within the hollow glass fiber is then cured to a solid state.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a substrate having a plurality of insulator layers and one or more conductive traces, wherein each of the insulator layers comprises a glass fiber substrate impregnated with a varnish coating, wherein the glass fiber substrate of one of the insulator layers includes one or more low-Dk-core glass fibers each having a low dielectric constant (Dk) core comprising either a low Dk fluid core sealed within a hollow glass fiber shell or a low Dk solid core surrounded by a hollow glass fiber shell, and wherein the Dk value of the low Dk core is less than that of the hollow glass fiber shell. 2. The apparatus as recited in claim 1 , wherein a plurality of through-holes each of which extends completely through the substrate from a first surface of the substrate to a second surface of the substrate and passes through the glass fiber substrate of each of the insulator layers, and wherein the one or more low-Dk-core glass fibers extends from a first one of the through-holes to a second one of the through-holes; a silane polymer barrier layer formed over a first end of each of the one or more low-Dk-core glass fibers in the first one of the through-holes; a silane polymer barrier layer formed over a second end of each of the one or more low-Dk-core glass fibers in the second one of the through-holes; wherein the silane polymer barrier layer formed over the first end of the one or more low-Dk-core glass fibers and the silane polymer barrier layer formed over the second end of the one or more low-Dk-core glass fibers seal the low Dk fluid within the hollow glass fiber shell. 3. The apparatus as recited in claim 2 , wherein a first plated through-hole (PTH) via is formed in the first one of the through-holes and a second plated through-hole (PTH) via is formed in the second one of the through-holes, and wherein the first PTH via operates at a voltage higher than that of the second PTH via such that the first and second PTHs together comprise an anode/cathode pair. 4. The apparatus as recited in claim 2 , wherein the apparatus is a printed circuit board (PCB). 5. The apparatus as recited in claim 4 , wherein the glass fiber substrate is a glass cloth constructed of glass fiber bundles woven together in an orthogonal fashion, and wherein the glass fiber bundles include a plurality of the low-Dk-core glass fibers. 6. The apparatus as recited in claim 5 , wherein the varnish coating is selected from a group of materials consisting of an epoxy-based resin, a bismaleimide triazine (BT) resin, a polyphenylene oxide/triallylisocyanurate (TAIC) composition, and combinations thereof. 7. The apparatus as recited in claim 1 , wherein a plurality of via holes each of which extends at least partially through the substrate and passes through the glass fiber substrate of at least one of the insulator layers, and wherein the one or more low-Dk-core glass fibers extends from a first one of the via holes to a second one of the via holes; a silane polymer barrier layer formed over a first end of each of the one or more low-Dk-core glass fibers in the first one of the via holes; a silane polymer barrier layer formed over a second end of each of the one or more low-Dk-core glass fibers in the second one of the via holes; wherein the silane polymer barrier layer formed over the first end of the one or more low-Dk-core glass fibers and the silane polymer barrier layer formed over the second end of the one or more low-Dk-core glass fibers seal the low Dk fluid within the hollow glass fiber shell. 8. The apparatus as recited in claim 7 , wherein a first plated through-hole (PTH) via is formed in the first one of the via holes and a second plated through-hole (PTH) via is formed in the second one of the via holes, and wherein the first PTH via operates at a voltage higher than that of the second PTH via such that the first and second PTHs together comprise an anode/cathode pair. 9. The apparatus as recited in claim 7 , wherein the apparatus is a printed circuit board (PCB). 10. The apparatus as recited in claim 9 , wherein the glass fiber substrate is a glass cloth constructed of glass fiber bundles woven together in an orthogonal fashion, and wherein the glass fiber bundles include a plurality of the low-Dk-core glass fibers. 11. The apparatus as recited in claim 10 , wherein the varnish coating is selected from a group of materials consisting of an epoxy-based resin, a bismaleimide triazine (BT) resin, a polyphenylene oxide/triallylisocyanurate (TAIC) composition, and combinations thereof. 12. An apparatus, comprising: a substrate having a plurality of insulator layers and one or more conductive traces, wherein each of the insulator layers comprises a glass fiber substrate impregnated with a varnish coating, wherein the glass fiber substrate of one of the insulator layers includes one or more low-Dk-core glass fibers each having a low dielectric constant (Dk) core comprising a low Dk fluid core sealed within a hollow glass fiber shell, and wherein the Dk value of the low Dk core is less than that of the hollow glass fiber shell. 13. An apparatus, comprising: a substrate having a plurality of insulator layers and one or more conductive traces, wherein each of the insulator layers comprises a glass fiber substrate impregnated with a varnish coating, wherein the glass fiber substrate of one of the insulator layers includes one or more low-Dk-core glass fibers each having a low dielectric constant (Dk) core comprising a low Dk solid core surrounded by a hollow glass fiber shell, and wherein the Dk value of the low Dk core is less than that of the hollow glass fiber shell.

Assignees

Inventors

Classifications

  • Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

  • Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

  • Sealing or impregnating, e.g. of pores · CPC title

  • Polysiloxanes · CPC title

  • from molten glass in which the resultant product consists of different sorts of glass or is characterised by shape, e.g. hollow fibres {, undulated fibres, fibres presenting a rough surface (C03B37/025 takes precedence)} · CPC title

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What does patent US9456496B2 cover?
An enhanced substrate for use in printed circuit boards (PCBs) includes low-Dk-core glass fibers having low dielectric constant (Dk) cores. In some embodiments, the low-Dk-core glass fibers are filled with a low Dk fluid, such as a gas (e.g., air, nitrogen and/or a noble gas) or a liquid. After via holes are drilled or otherwise formed in the substrate, silane is applied to the ends of hollow g…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H05K1/0366. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).