Three phase and polarity encoded serial interface

US9455850B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9455850-B2
Application numberUS-201514796207-A
CountryUS
Kind codeB2
Filing dateJul 10, 2015
Priority dateMar 2, 2007
Publication dateSep 27, 2016
Grant dateSep 27, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for decoding data, comprising: receiving a three-phase signal from each of three conductors of a communication link, wherein the three-phase signal must be transmitted on each of the three conductors in different phases; deriving a receive clock from transitions between encoding states of the three conductors; and decoding data from a sequence of encoding states of the three conductors using the receive clock, wherein during a first time interval of a first pair of sequential time intervals, no current flows in a first conductor of the three conductors while a current flows between a second conductor of the three conductors and a third conductor of the three conductors, wherein during a second time interval of the first pair of sequential time intervals: no current flows in the second conductor while a current flows between the first conductor and the third conductor when data to be encoded at a transition between the first pair of sequential time intervals has a first value, and no current flows in the third conductor while a current flows between the first conductor and the second conductor when the data to be encoded at the transition between the first pair of sequential time intervals has a second value, wherein N encoding states are defined for the communications link, including at least three encoding states defined by flow of current in the three conductors, wherein a change of encoding state to one of N−1 available encoding states occurs at each transition between sequential time intervals, and wherein N is an integer greater than or equal to six. 2. The method of claim 1 , wherein data is encoded in the change of encoding state at a transition between each pair of sequential time intervals. 3. The method of claim 2 , wherein current flows in a pair of conductors correspond to a first voltage level on one conductor and a second voltage level on another conductor, and wherein data is decoded based on a polarity of a difference between the first voltage level and the second voltage level. 4. The method of claim 1 , wherein data is decoded based on a direction of flow of current in a pair of conductors. 5. The method of claim 1 , wherein 16 bits of data are decoded from 8 or fewer transitions between sequential time intervals. 6. The method of claim 1 , wherein: during a first time interval of a second pair of sequential time intervals, a current flows in a first direction between a pair of conductors of the three conductors while no current flows in a remaining conductor of the three conductors, and during a second time interval of the second pair of sequential time intervals, a current flows in a second direction between the pair of conductors while no current flows in the remaining conductor. 7. The method of claim 1 , wherein current flows in a pair of conductors correspond to a first voltage level on one conductor and a second voltage level on another conductor, and wherein decoding data is based on a polarity of a difference between the first voltage level and the second voltage level, thereby defining N=6 possible encoding states. 8. The method of claim 7 , wherein up to log 2 (5) bits are encoded per transition between each pair of sequential time intervals. 9. An apparatus for decoding data, comprising: means for receiving a three-phase signal from each of three conductors of a communication link, wherein the three-phase signal must be transmitted on each of the three conductors in different phases; means for deriving a receive clock from transitions between encoding states of the three conductors; and means for decoding data from a sequence of encoding states of the three conductors using the receive clock, wherein during a first time interval of a first pair of sequential time intervals, no current flows in a first conductor of the three conductors while a current flows between a second conductor of the three conductors and a third conductor of the three conductors, wherein during a second time interval of the first pair of sequential time intervals: no current flows in the second conductor while a current flows between the first conductor and the third conductor when data to be encoded at a transition between the first pair of sequential time intervals has a first value, and no current flows in the third conductor while a current flows between the first conductor and the second conductor when the data to be encoded at the transition between the first pair of sequential time intervals has a second value, wherein N encoding states are defined for the communications link, including at least three encoding states defined by flow of current in the three conductors, wherein a change of encoding state to one of N−1 available encoding states occurs at each transition between sequential time intervals, and wherein N is an integer greater than or equal to six. 10. The apparatus of claim 9 , wherein data is encoded in the change of encoding state at a transition between each pair of sequential time intervals. 11. The apparatus of claim 10 , wherein current flows in a pair of conductors correspond to a first voltage level on one conductor and a second voltage level on another conductor, and wherein the means for decoding data is configured to decode data based on a polarity of a difference between the first voltage level and the second voltage level. 12. The apparatus of claim 9 , wherein the means for decoding data is configured to decode data based on a direction of flow of current in a pair of conductors. 13. The apparatus of claim 9 , wherein 16 bits of data are decoded from 8 or fewer transitions between sequential time intervals. 14. The apparatus of claim 9 , wherein: during a first time interval of a second pair of sequential time intervals, a current flows in a first direction between a pair of conductors of the three conductors while no current flows in a remaining conductor of the three conductors, and during a second time interval of the second pair of sequential time intervals, a current flows in a second direction between the pair of conductors while no current flows in the remaining conductor. 15. The apparatus of claim 9 , wherein current flows in a pair of conductors correspond to a first voltage level on one conductor and a second voltage level on another conductor, and wherein the means for decoding data is configured to decode data based on a polarity of a difference between the first voltage level and the second voltage level, wherein N=6 possible encoding states are defined. 16. An apparatus that decodes data from multiple connectors of a communication interface, comprising: a processing circuit configured to: receive a three-phase signal from each of three conductors of a communication link, wherein the three-phase signal must be transmitted on each of the three conductors in different phases; derive a receive clock from transitions between encoding states of the three conductors; and decode data from a sequence of encoding states of the three conductors using the receive clock, wherein during a first time interval of a first pair of sequential time intervals, no current flows in a first conductor of the three conductors while a current flows between a second conductor of the three conductors and a third conductor of the three conductors, wherein during a second time interval of the first pair of sequential time intervals: no current flows in the second conductor while a current flows between the first conductor and the third conductor when data to be encoded at a transition between the first pair of seq

Assignees

Inventors

Classifications

  • using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

  • Provision for current-mode coupling · CPC title

  • Arrangement for terminating transmission lines · CPC title

  • Demodulator circuits; Receiver circuits · CPC title

  • Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9455850B2 cover?
A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed seri…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H04L5/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).