ΔΣ modulator and program of ΔΣ modulator

Patent metadata

Field	Value
Publication number	US-9455736-B2
Application number	US-201514957971-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 22, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

There is provided a ΔΣ modulator including a loop filter for inputting an m-value digital signal into a subtractor, an n-value quantizer for inputting a first output signal to be output from the loop filter and outputting a second output signal as an n-value digital signal, and a selecting device for inputting the first output signal and the second output signal therein, feeding back the first output signal to a subtractor of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to the subtractor of the loop filter when the absolute value is less than a predetermined value. The predetermined value in the selecting device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

First claim

What is claimed is:

1. A ΔΣ modulator for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) digital signal and outputting the n-value output signal, the ΔΣ modulator comprising:
a loop filter including a plurality of cascaded integrators each having a subtractor at its input, for inputting the m-value digital signal into the subtractor at a first integrator in the plurality of cascaded integrators;
an n-value quantizer for inputting a first output signal output from the loop filter and outputting a second output signal that is the n-value digital signal, the first output signal based on an output of a last integrator in the plurality of cascaded integrators; and
a selecting device for inputting the first output signal and the second output signal therein and selecting between feeding back the first output signal and the second output signal based on the first output signal and not based on outputs of the first integrator to next-to-last integrator in the plurality of cascaded integrators, and feeding back the first output signal to all of the subtractors of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to all of the subtractors of the loop filter when the absolute value of the first output signal is less than a predetermined value, wherein
the predetermined value in the selecting device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

2. The ΔΣ modulator according to claim 1 , wherein when n=2, in the n-value quantizer, a threshold with respect to the input signal for deciding a signal value of a binary digital signal to be output to a first quantization value or a second quantization value is set to zero.

3. The ΔΣ modulator according to claim 2 , wherein when n=2, the first quantization value and the second quantization value of the n-value quantizer are set as positive and negative quantization values of which absolute values are equal to each other.

4. A non-transitory computer readable medium storing a program for causing a computer to execute ΔΣ modulation signal processing for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) digital signal and outputting the n-value digital signal, the program causing a processor of the computer to execute:
a step of executing signal processing in a loop filter for inputting the m-value digital signal into a subtractor, the loop filter including a plurality of cascaded integrators each having a subtractor at its input, wherein the m-value digital signal is input into the subtractor at a first integrator in the plurality of cascaded integrators, and the loop filter outputs a first output signal based on an output of a last integrator in the plurality of cascaded integrators;
a step of executing n-value quantization signal processing for inputting the first output signal to be output from the loop filter and outputting a second output signal as the n-value digital signal; and
a step of executing selection processing for inputting the first output signal and the second output signal and selecting between feeding back the first output signal and the second output signal based on the first output signal and not based on outputs of the first integrator to next-to-last integrator in the plurality of cascaded integrators, feeding back the first output signal to all of the subtractors of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to all of the subtractors of the loop filter when the absolute value of the first output signal is less than a predetermined value, wherein
the predetermined value in the selection processing is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

5. A ΔΣ modulator for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) digital signal and outputting the n-value output signal, the ΔΣ modulator comprising:
a loop filter including a plurality of cascaded integrators each having a subtractor at its input, for inputting the m-value digital signal into the subtractor at a first integrator in the plurality of cascaded integrators;
a y-value quantizer for inputting a first output signal to be output from the loop filter and outputting a second output signal as a y-value (y: an integer of 2 or more that satisfies m≧y≧n) digital signal, the first output signal based on an output of a last integrator in the plurality of cascaded integrators;
a selecting device for inputting the first output signal and the second output signal therein and selecting between feeding back the first output signal and the second output signal based on the first output signal and not based on outputs of the first integrator to next-to-last integrator in the plurality of cascaded integrators, feeding back the first output signal to all of the subtractors of the loop filter when an absolute value of the first output signal is a predetermined value or more, and feeding back the second output signal to all of the subtractors of the loop filter when the absolute value of the first output signal is less than a predetermined value; and
a ΔΣ modulating unit for inputting a signal fed back to the loop filter by the selection device and outputting the n-value digital signal, wherein
the predetermined value in the selection device is set to be larger than a maximum value of an absolute value of a quantization value to be obtained by the n-value digital signal.

6. The ΔΣ modulator according to claim 5 , wherein when n=2, the ΔΣ modulating unit is a first order ΔΣ modulating unit for executing first order ΔΣ modulation signal processing or a second order ΔΣ modulating unit for executing second order ΔΣ modulation signal processing.

7. The ΔΣ modulator according to claim 5 , wherein when n=y=2, a threshold with respect to an input signal for deciding a signal value of a binary digital signal output by the y-value quantizer is set to a first quantization value or a second quantization value.

8. The ΔΣ modulator according to claim 7 , wherein when n=y=2, the first quantization value and the second quantization value of the y-value quantizer are set as positive and negative quantization values of which absolute values are equal to each other.

9. A non-transitory computer readable medium storing a program for causing a computer to execute ΔΣ modulation signal processing for converting an m-value (m: an integer of 3 or more) digital signal into an n-value (n: an integer of 2 or more smaller than m) digital signal and outputting the n-value digital signal, the program causing a processor of the computer to execute:
a step of executing signal processing in a loop filter for inputting the m-value digital signal into a subtractor, the loop filter including a plurality of cascaded integrators each having a subtractor at its input, wherein the m-value digital signal is input into the subtractor at a first integrator in the plurality of cascaded integrators, and the loop filter outputs a first output signal based on an output of a last integrator in the plurality of cascaded integrators;
a step of executing y-value quantization signal processing for inputting the first output signal to be output from the loop filter and outputting a second output signal as a y-value digital signal;
a step of executing selection processing for inputting the first output signal and the secon

Assignees

• Onkyo Kk

Inventors

• Tachimori Nobuya

Classifications

• H03M3/424 Primary

  the quantiser being a multiple bit one · CPC title

• H03M7/3011 Primary

  of non-linear distortion, e.g. by temporarily adapting the operation upon detection of instability conditions (avoiding instability by structural design H03M7/3035) · CPC title

• H03M7/3026

  the quantiser being a multiple bit one · CPC title

• H03M7/304

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title