Current source array

Patent metadata

Field	Value
Publication number	US-9455689-B2
Application number	US-201414547684-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Nov 20, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

First claim

The invention claimed is:

1. A Silicon On Insulator (SOI) current source array comprising:
an input control configured to receive a control voltage;
a first reference input configured to receive a first reference voltage;
a second reference input configured to receive a second reference voltage;
a plurality of load circuits coupled to the second reference input;
a chain of SOI MOS transistors of a same type and each having a control electrode coupled to the input control, a first conduction electrode coupled to the first reference input, and a second conduction electrode coupled to the second reference input via a respective load circuit configured to conduct a current when the chain of SOI MOS transistors are active upon application of the control voltage on the input control;
an insulating buried layer located below the chain of SOI MOS transistors;
a semiconductor well located below the insulating buried layer; and
an input bias circuit coupled to the semiconductor well located below the insulating buried layer below the chain of SOI MOS transistors to receive a biasing voltage, and each transistor body of the chain of SOI MOS transistors being electrically coupled to the input bias circuit through the semiconductor well.

2. The SOI current source array according to claim 1 , wherein said input bias circuit comprises:
a first semiconductor contact region to receive a first biasing voltage and coupled to a first zone of the semiconductor well located below a first transistor of the chain;
a second semiconductor contact region to receive a second biasing voltage and coupled to a second zone of the semiconductor well located below a last transistor of the chain; and
a resistive zone of said semiconductor well extending between and mutually coupling the first and second zones.

3. The SOI current source array according to claim 1 , wherein each of the SOI MOS transistors have a same channel width and channel length.

4. The SOI current source array according to claim 1 , wherein a space between two SOI MOS transistors of the chain of SOI MOS transistors is the same.

5. The SOI current source array according to claim 1 , wherein the chain of SOI MOS transistors comprises a chain of Ultra Thin Body and Box Silicon On Insulator (UTBB FDSOI) transistors to define a UTBB FDSOI current source array.

6. An integrated circuit comprising:
a Silicon On Insulator (SOI) current source array including
an input control configured to receive a control voltage,
a first reference input configured to receive a first reference voltage,
a second reference input configured to receive a second reference voltage,
a plurality of load circuits coupled to the second reference input,
a chain of SOI MOS transistors of the same type and each having a control electrode coupled to the input control, a first conduction electrode coupled to the first reference input, and a second conduction electrode coupled to the second reference input via a respective load circuit configured to conduct a current when the chain of SOI MOS transistors are active upon application of the control voltage on the input control,
an insulating buried layer located below the chain of SOI MOS transistors,
a semiconductor well located below the insulating buried layer, and
an input bias circuit coupled to the semiconductor well located below the insulating buried layer below the chain of SOI MOS transistors to receive a biasing voltage, and each transistor body of the chain of SOI MOS transistors being electrically coupled to the input bias circuit through the semiconductor well.

7. The integrated circuit according to claim 6 , wherein said input bias circuit comprises:
a first semiconductor contact region to receive a first biasing voltage and coupled to a first zone of the semiconductor well located below a first transistor of the chain;
a second semiconductor contact region to receive a second biasing voltage and coupled to a second zone of the semiconductor well located below a last transistor of the chain; and
a resistive zone of said semiconductor well extending between and mutually coupling the first and second zones.

8. The integrated circuit according to claim 6 , wherein each of the SOI MOS transistors have a same channel width and channel length.

9. The integrated circuit according to claim 6 , wherein a space between two SOI MOS transistors of the chain of the SOI MOS transistors is the same.

10. The integrated circuit according to claim 6 , wherein the chain of SOI MOS transistors comprises a chain of Ultra Thin Body and Box Silicon On Insulator (UTBB FDSOI) transistors to define a UTBB FDSOI current source array.

11. A method of making a Silicon On Insulator (SOI) current source array, the method comprising:
providing an input control configured to receive a control voltage, a first reference input configured to receive a first reference voltage, and a second reference input configured to receive a second reference voltage;
forming a chain of SOI MOS transistors of the same type and each having a control electrode coupled to the input control, a first conduction electrode coupled to the first reference input, and a second conduction electrode coupled to the second reference input via a respective load circuit configured to conduct a current when the chain of SOI MOS transistors are active upon application of the control voltage on the input control;
forming an insulating buried layer below the chain of SOI MOS transistors;
forming a semiconductor well located below the insulating buried layer; and
coupling an input bias circuit to the semiconductor well located below the insulating buried layer below the chain of SOI MOS transistors to receive a biasing voltage, and each transistor body of the chain of SOI MOS transistors being electrically coupled to the input bias circuit through the semiconductor well.

12. The method according to claim 11 , wherein the input bias circuit comprises:
a first semiconductor contact region to receive a first biasing voltage and coupled to a first zone of the semiconductor well located below a first transistor of the chain;
a second semiconductor contact region to receive a second biasing voltage and coupled to a second zone of the semiconductor well located below a last transistor of the chain; and
a resistive zone of said semiconductor well extending between and mutually coupling the first and second zones.

13. The method according to claim 11 , wherein each of the SOI MOS transistors have a same channel width and channel length.

14. The method according to claim 11 , wherein a space between two SOI MOS transistors of the chain of the SOI MOS transistors is the same.

15. The method according to claim 11 , wherein the chain of SOI MOS transistors comprises a chain of Ultra Thin Body and Box Silicon On Insulator (UTBB FDSOI) transistors to define a UTBB FDSOI current source array.

Assignees

• St Microelectronics Sa
• Univ Of Twente

Inventors

• Cathelin Andreia
• Nauta Bram

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01 Primary

  Manufacture or treatment · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title