Junctionless semiconductor device having buried gate, apparatus including the same, and method for manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-9455329-B2
Application number	US-201414553811-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Aug 31, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.

First claim

What is claimed is:

1. A method for forming a junctionless semiconductor device, the method comprising:
providing a substrate including a lower silicon layer, an insulation film, and an upper silicon layer;
forming a device-isolation trench that defines an active region by etching the upper silicon layer and the insulation film, which are formed over the lower silicon layer;
forming a device isolation film by filling the device isolation trench with an insulation material;
implanting the same-type impurities into the entirety of the active region including a body and source and drain regions; and
forming a plurality of buried gates in the active region and the device isolation film,
wherein the implanting of the impurities includes:
implanting the impurities into the active region so that the active region has substantially uniform density.

2. The method according to claim 1 , wherein the insulation film includes a buried insulation film formed by burying an insulation material within a semiconductor substrate so that the semiconductor substrate is divided into the upper silicon layer and the lower silicon layer.

3. The method according to claim 1 , wherein the implanting of the impurities includes:
implanting the same-type impurities into a source, a drain, and a body of a transistor formed in the active region.

4. The method according to claim 1 , wherein the implanting of the impurities includes:
implanting the impurities using at least one of a multi-stage ion implanting process, a tilted ion implanting process, and a rotating ion implanting process.

5. The method according to claim 1 , wherein the implanting of the impurities includes:
implanting the impurities into the active region before forming the device isolation film.

6. The method according to claim 1 , wherein the implanting of the impurities includes:
implanting the impurities into the active region after forming the device isolation film.

7. The method according to claim 1 , wherein the implanting of the impurities includes:
forming a plurality of gate recesses in which the buried gates are to be formed by etching the active region and the device isolation film; and
implanting the impurities into the active region through the gate recesses.

8. The method according to claim 7 , wherein the forming of the gate recesses includes:
forming a fin structure in which the active region more protrudes than the device isolation film from the lower silicon layer.

Assignees

• Sk Hynix Inc

Inventors

• Min Kyung Kyu
• Yoo Min Soo
• Kwon Il Woong

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D30/6218

  of the accumulation type · CPC title

• G11C8/10

  Decoders · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title