Display device and driving method thereof

US9455311B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9455311-B2
Application numberUS-201514933745-A
CountryUS
Kind codeB2
Filing dateNov 5, 2015
Priority dateOct 18, 2005
Publication dateSep 27, 2016
Grant dateSep 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a third period, a voltage based on a video signal voltage and the threshold voltage of the first transistor is held in the first and second storage capacitors; and in a fourth period, voltages held in the first and second storage capacitors are applied to a gate terminal of the first transistor to supply a current to a light-emitting element, so that the light-emitting element emits light. Through the operation process, a current obtained by compensating variations in the threshold voltage of the first transistor can be supplied to the light-emitting element, thereby variations in luminance can be suppressed.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a transistor; a capacitor; a first switch; a second switch; a third switch; and a fourth switch; wherein a conductive layer comprises a region serving as a gate of the transistor and a region serving as a first electrode of the capacitor, wherein one of a source and a drain of the transistor is electrically connected to a third wiring, wherein a first terminal of the first switch is electrically connected to the gate of the transistor through a second conductive layer, wherein a second terminal of the first switch is electrically connected to the other of the source and the drain of the transistor, wherein a first terminal of the second switch is electrically connected to the other of the source and the drain of the transistor, wherein a second terminal of the second switch is electrically connected to a pixel electrode, wherein a first terminal of the third switch is electrically connected to a first wiring, wherein a second terminal of the third switch is electrically connected to a semiconductor layer comprising a region serving as a second electrode of the capacitor, wherein a first terminal of the fourth switch is electrically connected to a second wiring, and wherein a second terminal of the fourth switch is electrically connected to the second electrode. 2. The semiconductor device according to claim 1 , wherein the second terminal of the third switch is electrically connected to the semiconductor layer through a third conductive layer. 3. The semiconductor device according to claim 2 , wherein the transistor comprises a channel formation region comprising polysilicon. 4. The semiconductor device according to claim 2 , wherein the first switch, the second switch, the third switch, and the fourth switch are a second transistor, a third transistor, a fourth transistor, and a fifth transistor, respectively, and wherein a ratio of a channel width to a channel length in the transistor is larger than a ratio of a channel width to a channel length in the second transistor, a ratio of a channel width to a channel length in the third transistor, a ratio of a channel width to a channel length in the fourth transistor, and a ratio of a channel width to a channel length in the fifth transistor. 5. The semiconductor device according to claim 1 , wherein a light-emitting element comprises the pixel electrode. 6. The semiconductor device according to claim 5 , wherein the second terminal of the third switch is electrically connected to the semiconductor layer through a third conductive layer. 7. The semiconductor device according to claim 1 , wherein the transistor comprises a channel formation region comprising polysilicon. 8. The semiconductor device according to claim 1 , wherein the first switch, the second switch, the third switch, and the fourth switch are a second transistor, a third transistor, a fourth transistor, and a fifth transistor, respectively, and wherein a ratio of a channel width to a channel length in the transistor is larger than a ratio of a channel width to a channel length in the second transistor, a ratio of a channel width to a channel length in the third transistor, a ratio of a channel width to a channel length in the fourth transistor, and a ratio of a channel width to a channel length in the fifth transistor. 9. A semiconductor device comprising: a transistor; a light-emitting element; a first capacitor whose first electrode is electrically connected to a gate of the transistor; a second capacitor whose first electrode is electrically connected to the gate of the transistor; a first switch capable of controlling conduction and non-conduction between the gate of the transistor and one of a source and a drain of the transistor a second switch capable of controlling conduction and non-conduction between the one of a source and a drain of the transistor and a first electrode of the light-emitting element; a first wiring capable of transmitting a video signal; a third switch capable of controlling conduction and non-conduction between the first wiring and a second electrode of the first capacitor; a second wiring capable of transmitting a potential lower than a potential of the other of the source and the drain of the transistor; a fourth switch capable of controlling conduction and non-conduction between the second wiring and the second electrode of the first capacitor; and a fifth switch capable of controlling conduction and non-conduction between the second electrode of the first capacitor and the one of the source and the drain of the transistor; wherein a second electrode of the second capacitor is electrically connected to the second wiring, and wherein a potential of the other of the source and the drain of the transistor is higher than a potential of a second electrode of the light-emitting element. 10. An electronic device comprising the semiconductor device according to claim 9 . 11. The semiconductor device according to claim 9 , wherein the transistor comprises a channel formation region comprising polysilicon. 12. The semiconductor device according to claim 9 , wherein the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and a sixth transistor, respectively, and wherein a ratio of a channel width to a channel length in the transistor is larger than a ratio of a channel width to a channel length in the second transistor, a ratio of a channel width to a channel length in the third transistor, a ratio of a channel width to a channel length in the fourth transistor, a ratio of a channel width to a channel length in the fifth transistor, and a ratio of a channel width to a channel length in the sixth transistor.

Assignees

Inventors

Classifications

  • Interconnections, e.g. wiring lines or terminals · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • characterised by the doping profiles, e.g. having lightly-doped source or drain extensions · CPC title

  • having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs · CPC title

  • Interconnections, e.g. scanning lines · CPC title

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What does patent US9455311B2 cover?
To provide a display device and a driving method thereof, where variations in the threshold voltage of transistors can be compensated and thus variations in luminance of light-emitting elements can be suppressed. In a first period, initialization is performed; in a second period, a voltage based on the threshold voltage of a first transistor is held in first and second storage capacitors; in a …
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).