Imaging device, monitoring device, and electronic appliance

Patent metadata

Field	Value
Publication number	US-9455287-B2
Application number	US-201514749355-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jun 25, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A highly accurate imaging device or a highly accurate imaging device capable of detecting differences is provided. A configuration including a circuit in which variation in threshold voltage among amplifier transistors of pixels is corrected is employed. The configuration reduces variation in difference data due to variation in the threshold voltage among the amplifier transistors of the pixels to obtain highly accurate imaging data. Furthermore, charge corresponding to difference data between imaging data in an initial frame and imaging data in a current frame is accumulated in pixels and the difference data is read from each pixel, whereby highly accurate difference data is obtained when whether there is a difference between the initial frame and the current frame is determined.

First claim

What is claimed is:

1. An imaging device comprising a pixel, the pixel comprising:
a photodiode configured to generate photoelectric converted signal charge;
a first transistor;
a second transistor;
a first capacitor;
a second capacitor;
a first wiring configured to supply a low potential;
a second wiring configured to supply a high potential; and
a third wiring configured to supply a high potential,
wherein one electrode of the photodiode is electrically connected to the first wiring,
wherein one electrode of the first capacitor is electrically connected to the other electrode of the photodiode,
wherein the other electrode of the first capacitor is electrically connected to a gate of the first transistor,
wherein one electrode of the second capacitor is electrically connected to the gate of the first transistor,
wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor, and
wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring.

2. The imaging device according to claim 1 , further comprising a third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the other electrode of the photodiode,
wherein the other of the source and the drain of the third transistor is electrically connected to the one electrode of the first capacitor, and
wherein the third transistor is configured to supply the signal charge to the one electrode of the first capacitor.

3. The imaging device according to claim 2 ,
wherein the third transistor comprises a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

4. The imaging device according to claim 1 , further comprising:
a fourth transistor; and
a fourth wiring configured to supply a high potential,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the one electrode of the first capacitor, and
wherein the fourth transistor is configured to supply a potential of the fourth wiring to the one electrode of the first capacitor.

5. The imaging device according to claim 4 ,
wherein the fourth transistor comprises a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

6. The imaging device according to claim 1 ,
wherein the first and second transistors each comprise a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

7. The imaging device according to claim 1 ,
wherein the second transistor is configured to make the second capacitor have a threshold voltage of the first transistor by supplying a potential of the third wiring to the one electrode of the second capacitor, and
wherein the first capacitor is configured to bring the other electrode of the first capacitor into an electrically floating state in a state where the threshold voltage is retained in the second capacitor, and configured to change a potential of the gate of the first transistor when a potential of the one electrode of the first capacitor is changed in accordance with the signal charge.

8. A monitoring device comprising:
a camera comprising the imaging device according to claim 1 ;
a display device functionally connected to the camera;
a memory device functionally connected to the camera; and
an alarm device functionally connected to the camera.

9. An electronic appliance comprising:
the monitoring device according to claim 8 ; and
an operation key.

10. An imaging device comprising a pixel, the pixel comprising:
a photodiode configured to generate photoelectric converted signal charge;
a first transistor;
a second transistor;
a third transistor;
a first capacitor;
a second capacitor;
a third capacitor;
a first wiring configured to supply a low potential;
a second wiring configured to supply a high potential or a low potential;
a third wiring configured to supply a high potential; and
a fourth wiring configured to supply a high potential,
wherein one electrode of the photodiode is electrically connected to the first wiring,
wherein one electrode of the first capacitor is electrically connected to the other electrode of the photodiode,
wherein the other electrode of the first capacitor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein the other electrode of the second capacitor is electrically connected to a gate of the second transistor,
wherein one electrode of the third capacitor is electrically connected to the gate of the second transistor,
wherein the other electrode of the third capacitor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the gate of the second transistor, and
wherein the other of the source and the drain of the third transistor is electrically connected to the fourth wiring.

11. The imaging device according to claim 10 , further comprising a fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the other electrode of the photodiode,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the one electrode of the first capacitor, and
wherein the fourth transistor is configured to supply the signal charge to the one electrode of the first capacitor.

12. The imaging device according to claim 11 ,
wherein the fourth transistor comprises a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

13. The imaging device according to claim 10 , further comprising:
a fifth transistor; and
a fifth wiring configured to supply a high potential,
wherein one of a source and a drain of the fifth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the one electrode of the first capacitor, and
wherein the fifth transistor is configured to supply a potential of the fifth wiring to the one electrode of the first capacitor.

14. The imaging device according to claim 13 ,
wherein the fifth transistor comprises a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

15. The imaging device according to claim 10 ,
wherein the first to third transistors each comprise a semiconductor layer, and
wherein the semiconductor layer comprises an oxide semiconductor.

16. The imaging device according to claim 10 ,
wherein the third transistor is configured to make the third capacitor have a threshold voltage of the second transistor by supplying a potential of the fourth wiring to the one electrode of the third capacitor,
wher

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H10F39/8053 Primary

  Colour filters · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/6811

  based on the image signal · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title