Fixture to constrain laminate and method of assembly

Patent metadata

Field	Value
Publication number	US-9455234-B2
Application number	US-201414217537-A
Country	US
Kind code	B2
Filing date	Mar 18, 2014
Priority date	Sep 22, 2010
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

First claim

What is claimed:

1. A method of joining a chip on a laminate, comprising:
positioning a laminate having a top surface, a bottom surface and sides on a surface of a first plate of a fixture and directly abutting against at least two surfaces of a stepped feature;
positioning a second plate of the fixture on the top surface of the laminate;
mating the first plate and the second plate together;
placing a chip on the laminate; and
reflowing solder to connect the chip on the laminate,
wherein when the first plate and the second plate are mated and the laminate is directly abutting the at least two surfaces of the stepped feature, the laminate is constrained in X, Y, and Z directions during assembly processes,
wherein the stepped feature is provided on both the first plate and the second plate, and the second plate has a U-shaped stepped portion on the first plate in a plan view, and
wherein a coefficient of thermal expansion (CTE) of the fixture is such that the fixture expands less than the laminate to prevent expansion of the laminate.

2. The method of claim 1 , wherein the first plate and the second plate are mated by one or more mechanical fasteners.

3. The method of claim 1 , wherein the placing a chip on the laminate comprising placing the chip on the laminate through an opening in the first plate.

4. The method of claim 1 , wherein the first plate and the second plate apply pressure to the top surface, the bottom surface and all sides of the laminate to prevent expansion within the fixture.

5. The method of claim 1 , wherein a chip is bonded to the laminate by a process that requires heating and cooling of the chip and the laminate.

6. A method of joining a chip on a laminate, comprising:
mating a first plate of a fixture to a second plate of the fixture; and
providing a space defined by facing surfaces of the first plate and the second plate and confined by a stepped portion of at least one of the first plate and the second plate,
wherein:
the space is sized and shaped such that the laminate is confined within the space and directly abuts at least two surfaces of the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions,
wherein the stepped portion is provided on both the first plate and the second plate, and the second plate has a U-shaped stepped portion in a plan view, and
wherein a coefficient of thermal expansion (CTE) of the fixture is such that the fixture expands less than the laminate to prevent expansion of the laminate.

7. The method of claim 6 , wherein the first plate has an opening sized to accommodate a chip mounted on a laminate.

8. The method of claim 6 , wherein the second plate is mated to the first plate by at least one mechanical fastening mechanism.

9. The method assembly of claim 6 , wherein the stepped portion of the first plate and the stepped portion of the second plate form a closed area in the X and Y direction.

10. A method, comprising:
providing a first plate of a fixture having an opening; and
mating a second plate of the fixture to the first plate, such that when the first plate and the second plate are mated, a confined space is formed,
wherein, in the confined space, contact is made to a top surface of a laminate about a periphery and to a bottom surface of the laminate by the first plate and the second plate, respectively, and sides of the laminate by at least two surfaces of stepped features of the first plate and the second plate such that the laminate is constrained in X, Y, and Z directions during assembly processes,
wherein the stepped features are provided on both the first plate and the second plate, and the second plate has a U-shaped stepped portion in a plan view, and
wherein a coefficient of thermal expansion (CTE) of the fixture is such that the fixture expands less than the laminate to prevent expansion of the laminate.

11. The method of claim 10 , wherein the mating of the second plate with the first plate comprises mating the second plate to the stepped feature of the first plate, such that when the first plate and the second plate are mated the confined space is form with the stepped feature of the first plate.

12. The method of claim 1 , wherein the first plate of the fixture, the second plate of the fixture, and the laminate all have a substantially similar coefficient of thermal expansion (CTE).

13. The method of claim 1 , wherein the first plate of the fixture and the second plate of the fixture comprise at least one material of Invar, stainless steel, and machinable glass ceramic.

14. The method of claim 1 , wherein the U-shaped stepped portion extends an entirety of a length of the second plate.

15. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the laminate is about 17×10 6 /° C. and a coefficient of thermal expansion (CTE) of the chip is about 2.6×10 6 /° C.

16. The method of claim 1 , wherein the reflowing the solder to connect the chip on the laminate occurs at a reflow temperature between 235° C. and 255° C.

17. The method of claim 16 , wherein the reflowing the solder to connect the chip on the laminate occurs through a plan of record (POR) belt furnace to achieve the reflow temperature between 235° C. and 255° C.

Assignees

• IBM

Inventors

• Lombardi Thomas E
• Merte Donald
• Monjeau Gregg B
• Questad David L
• Tran Son K

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/07204

  using temporary auxiliary members, e.g. sacrificial coatings · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title