All-in-one power semiconductor module

Patent metadata

Field	Value
Publication number	US-9455207-B2
Application number	US-201313830122-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Oct 31, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate.
According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

First claim

What is claimed is:

1. An all-in-one power semiconductor module, comprising:
a plurality of first semiconductor devices formed on a substrate;
a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and
a plurality of lead members having a portion embedded in the bridges, directly bonded with the plurality of first semiconductor devices, and electrically connecting the plurality of first semiconductor devices and the substrate,
wherein at least one of the plurality of lead members is directly connected to at least one of the plurality of first semiconductor devices.

2. The all-in-one power semiconductor module as set forth in claim 1 , further comprising:
a plurality of second semiconductor devices formed on upper portions of the bridges.

3. The all-in-one power semiconductor module as set forth in claim 1 , wherein the plurality of first semiconductor devices have different heights, and lengths of the plurality of lead members are adjusted in such a way that a step difference with respect to the height of each of the plurality of first semiconductor devices is adjusted.

4. The all-in-one power semiconductor module as set forth in claim 1 , wherein the plurality of lead members have elasticity.

5. The all-in-one power semiconductor module as set forth in claim 1 , wherein the number of the plurality of first semiconductor devices is two, and lead members of a first voltage input terminal and a second voltage input terminal are connected to the two first semiconductor devices,
wherein the lead members of a power input terminal and the first voltage input terminal protrude from one side of the housing, and the lead members of a ground terminal and the second voltage input terminal protrude from another side of the housing.

6. The all-in-one power semiconductor module as set forth in claim 1 , wherein the plurality of first semiconductor devices and the plurality of lead frames are molded by resin.

7. The all-in-one power semiconductor module as set forth in claim 1 , wherein the housing includes:
first and second side wall members vertically disposed; and
first and second bridges disposed between the first and second side wall members and extending from the first and second side wall members at a right angle, respectively.

8. The all-in-one power semiconductor module as set forth in claim 7 , wherein a first housing formed of the first side wall member and the first bridge and a second housing formed of the second side wall member and the second bridge are diagonal to each other.

9. The all-in-one power semiconductor module as set forth in claim 4 , wherein the lead member of the power input terminal protrudes from one side of the housing, the lead members of the ground terminal and the second voltage input terminal protrude from another side of the housing, and the plurality of lead members connected to the plurality of first semiconductor devices are connected to a second substrate.

Assignees

• Samsung Electro Mech

Inventors

• Kim Kwang Soo
• Yang Si Joong
• Suh Bum Seok
• Kwak Young Hoon
• Ha Job

Classifications

• H10W72/07653

  changes in shapes · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/652

  comprising metals or metalloids, e.g. silver · CPC title

• H10W70/69

  Insulating materials thereof · CPC title