Semiconductor apparatus having TSV and testing method thereof

Patent metadata

Field	Value
Publication number	US-9455190-B2
Application number	US-201514822727-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Sep 3, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (TSV) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the TSV, wherein the first conductive layer is withdrawn into an upper surface of the wafer. The method may include measuring a voltage between the bump and the first conductive layer. The method may include comparing the measured voltage to a preset reference voltage. The method may include determining the TSV as a normal TSV in which no fail occurs, according a comparing result, and grinding the wafer to expose the rear surface of the TSV.

First claim

What is claimed is:

1. A test method of a semiconductor apparatus before a wafer is ground, comprising the steps of:
applying voltages to a bump electrically coupled to a through-silicon via (TSV) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the TSV, wherein the first conductive layer is withdrawn into an upper surface of the wafer;
measuring a voltage between the bump and the first conductive layer;
comparing the measured voltage to a preset reference voltage;
determining the TSV as a normal TSV in which no fail occurs, according a comparing result; and
grinding the wafer to expose the rear surface of the TSV.

2. The test method according to claim 1 , wherein a VDD voltage is applied to the bump, and a VSS voltage is applied to the conductive layer.

3. The test method according to claim 1 , further comprising the steps of:
determining whether or not the failed TSV can be repaired;
repairing the failed TSV using a redundancy TSV when the failed TSV can be repaired; and
classifying the failed TSV as a final failed TSV and discarding the failed TSV, when the failed TSV cannot be repaired.

4. The test method according to claim 1 , wherein the voltage between the bump and the conductive layer is measured by a voltage measuring block.

5. The test method according to claim 1 , wherein the voltage between the bump and the conductive layer is measured by a sense amplifier.

6. The test method according to claim 1 , wherein the voltage between the bump and the conductive layer is measured by a capacitance measuring block.

7. The test method according to claim 1 , further comprising the step of forming a package structure after determining the TSV as a normal TSV in which no fail occurs.

8. A test method of a semiconductor apparatus, comprising the steps of:
forming a through-silicon via (TSV) in a semiconductor substrate;
forming a test conductive layer to surround of a circumference of the TSV, with insulating from the TSV;
applying a first voltage to the TSV;
applying a second voltage being different from the first voltage to the test conductive layer;
determining a fail of the TSV using to a voltage between the first voltage and the second voltage;
grinding the semiconductor substrate to expose a rear surface of the TSV; and
packaging a resultant of the semiconductor substrate.

9. The test method according to claim 8 , further comprising the steps of:
determining whether or not the failed TSV can be repaired;
repairing the failed TSV using a redundancy TSV when the failed TSV can be repaired; and
classifying the failed TSV as a final failed TSV and discarding the failed TSV, when the failed TSV cannot be repaired.

Assignees

• Sk Hynix Inc

Inventors

• Cho Hyung Jun

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/222

  Multilayered bumps, e.g. a coating on top and side surfaces of a bump core · CPC title

• H10W72/234

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/221

  Structures or relative sizes · CPC title