Crystallization processing for semiconductor applications

US9455145B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9455145-B2
Application numberUS-201615016328-A
CountryUS
Kind codeB2
Filing dateFeb 5, 2016
Priority dateNov 30, 2009
Publication dateSep 27, 2016
Grant dateSep 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a semiconductor layer on a crystalline substrate; melting a portion of the semiconductor layer by exposing the semiconductor layer to a plurality of energy pulses, wherein the plurality of energy pulses melts the portion of the semiconductor layer to reach a melt end point a distance from an interface between the semiconductor layer and the crystalline substrate, wherein a buffer layer is defined between the melt end point and the interface; crystallizing the buffer layer by exposing the semiconductor layer to a first group of one or more energy pulses distinct from the plurality of energy pulses, wherein a crystal structure of the buffer layer is formed; and crystallizing the melted portion of the semiconductor layer by the first group of one or more energy pulses, wherein a crystal structure of the melted portion of the semiconductor layer is developed from the crystal structure of the buffer layer. 2. The method of claim 1 , wherein the plurality of energy pulses includes a second group of one or more energy pulses and a third group of one or more energy pulses. 3. The method of claim 2 , wherein a power delivered by the third group of one or more energy pulses is higher than a power delivered by the second group of one or more energy pulses. 4. The method of claim 2 , wherein a power delivered by the first group of one or more energy pulses is less than a power delivered by the second group of one or more energy pulses. 5. The method of claim 2 , wherein the second group of one or more energy pulses is separated from the third group of one or more energy pulses by a rest duration. 6. The method of claim 5 , wherein the rest duration allows partial refreezing of the melted portion of the semiconductor layer. 7. The method of claim 1 , wherein the semiconductor layer is doped. 8. A method of treating a substrate, comprising: forming a semiconductor layer on a crystalline substrate; identifying a first treatment zone on the semiconductor layer; melting a portion of the semiconductor layer by exposing the first treatment zone of the semiconductor layer to a plurality of energy pulses, wherein the plurality of energy pulses melts the portion of the semiconductor layer to reach a melt end point a distance from an interface between the semiconductor layer and the crystalline substrate, wherein a buffer layer is defined between the melt end point and the interface; crystallizing a portion of the buffer layer by exposing the first treatment zone of the semiconductor layer to a first group of one or more energy pulses distinct from the plurality of energy pulses, wherein a crystal structure of the portion of the buffer layer is formed; crystallizing the melted portion of the first treatment zone of the semiconductor layer by the first group of one or more energy pulses, wherein a crystal structure of the melted portion of the semiconductor layer is developed from the crystal structure of the portion of the buffer layer; identifying a second treatment zone; and repeating melting a portion of the semiconductor layer, crystallizing a portion of the buffer layer and crystallizing the melted portion of the second treatment zone. 9. The method of claim 8 , wherein the plurality of energy pulses includes a second group of one or more energy pulses and a third group of one or more energy pulses. 10. The method of claim 9 , wherein a power delivered by the third group of one or more energy pulses is higher than a power delivered by the second group of one or more energy pulses. 11. The method of claim 9 , wherein a power delivered by the first group of one or more energy pulses is less than a power delivered by the third group of one or more energy pulses. 12. The method of claim 9 , wherein a power delivered by the first group of one or more energy pulses is less than a power delivered by the second group of one or more energy pulses. 13. The method of claim 9 , wherein the second group of one or more energy pulses is separated from the third group of one or more energy pulses by a rest duration. 14. The method of claim 13 , wherein the rest duration allows partial refreezing of the melted portion of the semiconductor layer. 15. A method, comprising: forming a semiconductor layer on a crystalline substrate; melting a portion of the semiconductor layer by exposing the semiconductor layer to a plurality of energy pulses, wherein the plurality of energy pulses melts the portion of the semiconductor layer to reach a melt end point a distance from an interface between the semiconductor layer and the crystalline substrate, wherein the plurality of energy pulses includes a first energy pulse at a first intensity and a first group of one or more energy pulses at a second intensity greater than the first intensity, wherein a buffer layer is defined between the melt end point and the interface; crystallizing the buffer layer by exposing the semiconductor layer to a second group of one or more energy pulses distinct from the plurality of energy pulses, wherein a crystal structure of the buffer layer is formed; and crystallizing the melted portion of the semiconductor layer by the first group of one or more energy pulses, wherein a crystal structure of the melted portion of the semiconductor layer is developed from the crystal structure of the buffer layer. 16. The method of claim 15 , wherein the second group of one or more energy pulses each has a third intensity less than the second intensity. 17. The method of claim 15 , wherein the second group of one or more energy pulses each has a third intensity less than the first intensity. 18. The method of claim 15 , wherein the first energy pulse is separated from the first group of one or more energy pulses by a rest duration. 19. The method of claim 18 , wherein the rest duration allows partial refreezing of the melted portion of the semiconductor layer. 20. The method of claim 15 , wherein the first group of one or more energy pulses includes 10 energy pulses.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • Pulsed laser beam · CPC title

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What does patent US9455145B2 cover?
A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone,…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/3411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).