Apparatuses and methods for performing an exclusive or operation using sensing circuitry

Patent metadata

Field	Value
Publication number	US-9455020-B2
Application number	US-201514715161-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Jun 5, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

First claim

What is claimed:

1. A method, comprising:
determining, using sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells, an exclusive OR (XOR) value of data stored in a number of memory cells coupled to a first sense line of the pair without transferring the data from the array using an input/output line, wherein determining the XOR value comprises:
performing an AND operation on:
a resultant value of a NAND operation performed on a first data value stored in a first memory cell coupled to the first sense line and a second data value stored in a second memory cell coupled to the first sense line; and
a resultant value of an OR operation performed on the first data value and the second data value.

2. The method of claim 1 , wherein performing the NAND operation includes:
loading a compute component of the sensing circuitry with the first data value;
enabling an access line to which the second memory cell is coupled and a first pass transistor which results in a data value corresponding to an AND operation performed on the first and second data values being stored in the compute component, wherein the first pass transistor has a first source/drain region coupled to the first sense line; and
inverting the data value stored in the compute component, the inverted data value being the resultant value of the NAND operation.

3. The method of claim 2 , wherein inverting the data value stored in the compute component comprises:
enabling an invert transistor coupled to a cross coupled latch of the sensing circuitry and to the one of the pair of complementary sense lines.

4. The method of claim 2 , wherein loading the compute component coupled to the pair of complementary sense lines with the first data value comprises enabling a first access line and the pair of complementary sense lines.

5. The method of claim 2 , further comprising writing the resultant value of the NAND operation to a third memory cell coupled to the first sense line.

6. The method of claim 5 , wherein writing the resultant value of the NAND operation to the third memory cell comprises enabling the third access line.

7. The method of claim 2 , wherein performing the OR operation includes:
loading the compute component with the first data value; and
enabling the access line to which the second memory cell is coupled and a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines such that the resultant value of the OR operation is stored in the compute component.

8. The method of claim 5 , wherein performing the AND operation on the resultant value of the NAND operation and the resultant value of the OR operation includes:
enabling an access line to which the third memory cell storing the resultant value of the NAND operation is coupled; and
enabling the first pass transistor which results in a resultant value of the AND operation performed on the NAND resultant value and the OR resultant value being stored in the compute component, wherein the resultant value is the XOR value corresponding to the first and second data values.

9. The method of claim 1 , wherein the sensing circuitry comprises a sense amplifier and a compute component and wherein the method includes loading the compute component with the first data value.

10. An apparatus, comprising:
an array of memory cells storing data in a group of memory cells coupled to a sense line;
sensing circuitry coupled to the array and configured to perform an XOR operation on the data without transferring data out of the array via an input/output line, wherein the XOR operation includes:
a NAND operation performed on a data value stored in a first memory cell coupled to a first access line and a data value stored in a second memory cell coupled to a second access line, wherein a resultant value of the NAND operation is stored in a third memory cell coupled to a third access line;
an OR performed operation on the data values stored in the first and second memory cells; and
an AND operation performed on the resultant value of the NAND operation and a resultant value of the OR operation.

11. The apparatus of claim 10 , further comprising a controller configured to provide control signals to the sensing circuitry to perform the XOR operation.

12. The apparatus of claim 10 , further comprising a host configured to provide instructions executed by an on-die controller configured to provide control signals to the sensing circuitry to perform the XOR operation.

13. The apparatus of claim 10 , wherein the sensing circuitry comprises a sense amplifier and a compute component coupled to a pair of complementary sense lines comprising the sense line and a complementary sense line, and wherein the sensing circuitry is configured to receive a number of control signals to, in association with performing the NAND operation:
load the compute component with the first data value;
perform a first AND operation on the first data value and the second data value by enabling the second access line and only one of a first pass transistor coupled to one of the pair of complementary sense lines and a second pass transistor couple to the other of the pair of complementary sense lines which results in a resultant value of the first AND operation being stored in the compute component; and
invert the resultant value of the first AND operation stored in the compute component which results in the compute component storing a resultant value of the NAND operation.

14. The apparatus of claim 13 , wherein the sensing circuitry being configured to receive a number of control signals to, in association with performing the NAND operation, load the compute component by enabling the second access line, the first pass transistor, and the second pass transistor.

15. The apparatus of claim 10 , wherein the first, second, and third access lines are different access lines.

16. The apparatus of claim 10 , wherein the sensing circuitry comprises a sense amplifier and a compute component coupled to a pair of complementary sense lines comprising the sense line and a complementary sense line, and wherein the sensing circuitry is configured to receive a number of control signals to, in association with performing the OR operation:
load the compute component coupled to the sense line with the data value stored in the first memory cell; and
enable an access transistor corresponding to the second memory cell and activate only one of a pass transistor coupled to the sense line and a pass transistor coupled to the complementary sense line which results in a resultant value of the OR operation being stored in the compute component.

17. The apparatus of claim 10 , wherein the sensing circuitry comprises a sense amplifier and a compute component coupled to a pair of complementary sense lines comprising the sense line and a complementary sense line, and wherein the sensing circuitry is configured to receive a number of control signals to, in association with performing the AND operation:
enable an access transistor corresponding to the third memory cell; and
activate only one of a first pass transistor coupled to one of the pair of complementary sense lines and a second pass transistor couple to the other of the pair of complementary sense lines which results in a resultant value of the AND operation being stored in the compute component.

18. The apparatus of claim 17 , wherein the sensing circuitry is further configured to receive a number of control signals to, in association wit

Assignees

• Micron Technology Inc

Inventors

• Manning Troy A

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title