Operating characteristics of a semiconductor device

Patent metadata

Field	Value
Publication number	US-9455009-B2
Application number	US-201514616996-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Sep 15, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines;
a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate; and
a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate,
wherein the first well region is isolated from the second well region, and the first connection circuit and the second connection circuit comprise NMOS transistors,
each of the first well region and the second well region comprises a P well, and
the P well of the first well region and the P well of the second well region are formed in a same N well.

2. The semiconductor device of claim 1 , wherein a first well bias is applied to the first well region and a second well bias is applied to the second well region.

3. The semiconductor device of claim 2 , wherein the well bias applying circuit is configured to apply the first well bias of a negative potential to the first well region, and apply the second well bias of a ground voltage or the second well bias of a positive potential to the second well region.

4. The semiconductor device of claim 1 , further comprising:
a block selection circuit configured to output a block selection signal to the first and second connection circuits according to an address signal.

5. The semiconductor device of claim 4 , wherein the block selection circuit is configured to allow the block selection signal of the selected memory block and block selection signals of non-selected memory blocks that are output to have different positive potentials.

6. The semiconductor device of claim 5 , wherein the block selection signal of the selected memory block is output with a higher level than the block selection signals of the non-selected memory blocks.

7. The semiconductor device of claim 1 , further comprising:
an operating voltage applying circuit configured to apply operating voltages to operate the memory cells to the global select lines and the global word lines.

8. The semiconductor device of claim 7 , wherein the operating voltage applying circuit is configured to decrease voltages of non-selected global drain select lines to a ground voltage or a negative potential level after increasing voltages of the global select lines to a first level.

9. The semiconductor device of claim 1 , further comprising:
a discharge circuit configured to discharge a line transferring the block selection signal to the first and second connection circuits in response to a discharge signal, and installed in a third well region,
wherein the third well region is electrically coupled to the second well region.

10. The semiconductor device of claim 9 , wherein the discharge circuit comprises an NMOS transistor electrically coupled between the line and a discharge node, and configured to operate according to the discharge signal.

11. A semiconductor device, comprising:
a first connection circuit formed in a first well region of a substrate to electrically couple local select lines of a selected memory block and global select lines; and
a second connection circuit formed in a second well region of the substrate to electrically couple local word lines of the selected memory block and global word lines,
wherein the first well region is isolated from the second well region, and the first connection circuit and the second connection circuit comprise NMOS transistors,
the first well region comprises a first P well formed in a first N well of the substrate, and the second well region comprises a second P well formed in a second N well of the substrate, and
the first N well and the second N well are electrically coupled to each other.

12. The semiconductor device of claim 11 , wherein the first connection circuit comprises first transistors configured to electrically couple the local select lines and the global select lines in response to a block selection signal, and
the second connection circuit comprises second transistors configured to electrically couple the local select lines and the global word lines in response to the block selection signal.

13. The semiconductor device of claim 11 , wherein the first well region is configured to be formed on both sides of the second well region.

14. A semiconductor device, comprising:
a first connection circuit configured with first transistors to electrically couple select lines of a memory block to global select lines according to a block selection signal in a first well region; and
a second connection circuit configured with second transistors to electrically couple local word lines of the memory block to global word lines according to the block selection signal in a second well region,
wherein a first well bias having a negative potential is applied to the first well region, and a second well bias having a ground voltage or a positive potential is applied to the second well region.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun
• Lee Dong Hwan

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C8/12 Primary

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title