Error correction method and module for non-volatile memory

Patent metadata

Field	Value
Publication number	US-9454428-B2
Application number	US-201414554577-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 26, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.

First claim

What is claimed is:

1. An error correction method for a non-volatile memory, the method comprising:
receiving a codeword read from the non-volatile memory;
computing a reliability information for each bit of the codeword received; and
performing a soft-decision decoding (SDD) technique to decode the received codeword,
wherein the SDD technique comprises:
forming a set of test patterns based on the reliability information; and
determining whether to perform a hard-decision decoding (HDD) of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern.

2. The method according to claim 1 , wherein the SDD technique further comprises identifying a predetermined number of least reliable bits in the received codeword, and wherein said forming a set of test patterns comprises forming a set of test patterns with respect to the identified predetermined number of least reliable bits.

3. The method according to claim 1 , wherein said distance is a Hamming distance and said determining whether to perform a HDD of a test pattern comprises determining whether the Hamming distance between the test pattern and the candidate pattern is greater than a value, the value being the maximum number of bit errors correctable for the codeword.

4. The method according to claim 3 , further comprises performing the HDD of the test pattern only when the Hamming distance between the test pattern and the candidate pattern is determined to be greater than said value.

5. The method according to claim 4 , wherein said determining whether to perform a HDD of a test pattern is performed for each test pattern in the set of test patterns, and wherein for each test pattern when a set of candidate patterns exists having one or more candidate patterns:
compute one or more Hamming distances respectively between the test pattern and each candidate pattern in the set of candidate patterns; and
perform the HDD of the test pattern only when the one or more Hamming distances computed for the test pattern are all greater than said value.

6. The method according to claim 1 , wherein the reliability information for each bit indicates a likelihood that the bit received is accurate, and the reliability information is based on a log-likelihood ratio (LLR) approximated by:
LLR≈ y k −y k _ Threshold .

where y k is an analog signal of the codeword read from the non-volatile memory and y k —Threshold is a predetermined threshold value of y k .

7. The method according to claim 1 , wherein the codeword is a BCH code or a Hamming code.

8. The method according to claim 1 , wherein the codeword is an extended BCH code or an extended Hamming code, and the method further comprises:
performing a HDD of the received codeword, and
determining whether to perform the SDD technique to decode the received codeword based on whether the HDD of the received codeword is successful.

9. The method according to claim 2 , further comprising adaptively adjusting a parameter that controls the predetermined number of least reliable bits in the received codeword to be identified based on one or more factors affecting the raw bit error rate of the non-volatile memory.

10. The method according to claim 9 , wherein the factors comprise a build-in self test result of the non-volatile memory, a temperature of the non-volatile memory, and a program cycle of the non-volatile memory.

11. An error correction module for a non-volatile memory, the error correction module comprises:
a reliability detector configured to receive a codeword read from the non-volatile memory and compute a reliability information for each bit of the codeword received; and
a soft-decision decoder configured to decode the received codeword,
wherein the soft-decision decoder is configured to:
form a set of test patterns based on the reliability information; and
determine whether to perform a hard-decision decoding (HDD) of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern.

12. The error correction module according to claim 11 , wherein the soft-decision decoder is further configured to identify a predetermined number of least reliable bits in the received codeword, and wherein the set of test patterns is formed with respect to the identified predetermined number of least reliable bits.

13. The error correction module according to claim 11 , wherein said distance is a Hamming distance and the soft-decision decoder configured to determine whether to perform a HDD of a test pattern comprises determining whether the Hamming distance between the test pattern and the candidate pattern is greater than a value, the value being the maximum number of bit errors correctable for the codeword.

14. The error correction module according to claim 13 , wherein the soft-decision decoder is further configured to perform the HDD of the test pattern only when the Hamming distance between the test pattern and the candidate pattern is determined to be greater than said value.

15. The error correction module according to claim 14 , wherein the soft-decision decoder is configured to determine whether to perform a HDD of a test pattern for each test pattern in the set of test patterns, and wherein for each test pattern when a set of candidate patterns exists having one or more candidate patterns, the soft-decision decoder is configured to:
compute one or more Hamming distances respectively between the test pattern and each candidate pattern in the set of candidate patterns; and
perform the HDD of the test pattern only when the one or more Hamming distances computed for the test pattern are all greater than said value.

16. The error correction module according to claim 11 , wherein the reliability information for each bit indicates a likelihood that the bit received is accurate, and the reliability information is based on a log-likelihood ratio (LLR) approximated by:
LLR≈ y k −y k _ Threshold ,

where y k is an analog signal of the codeword read from the non-volatile memory and Y k _ Threshold is a predetermined threshold value of y k .

17. The error correction module according to claim 11 , wherein the codeword is a BCH code or a Hamming code.

18. The error correction module according to claim 11 , wherein the codeword is an extended BCH or an extended Hamming code, and the soft-decision decoder is further configured to perform a HDD of the received codeword, and determine whether to perform the SDD technique to decode the received codeword based on whether the HDD of the received codeword is successful.

19. The error correction module according to claim 12 , wherein the soft-decision decoder is further configured to adaptively adjust a parameter that controls the predetermined number of least reliable bits in the received codeword to be identified in the received codeword based on one or more factors affecting the raw bit error rate of the non-volatile memory.

20. A memory system with error correction, the memory system comprising:
an encoder for encoding an input data into one or more codewords having error correction bits;
a non-volatile memory for storing the one or more codewords; and
an error correction module for decoding the codeword read from the non-volatile memory, the error correction module comprising:
a reliability detector configured to receive a codeword read from the non-volatile memory and compute a reliability information for each bit of the codeword received; and

Assignees

• Agency Science Tech & Res

Inventors

• Cai Kui
• Qin Zhiliang
• Wang Xueqiang

Classifications

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• H03M13/451

  using a set of candidate code words, e.g. ordered statistics decoding [OSD] · CPC title

• H03M13/458

  by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result · CPC title