Array printed circuit board, method of replacing defective single printed circuit board of the same, and method of manufacturing electronic apparatus using the same

Patent metadata

Field	Value
Publication number	US-9451691-B2
Application number	US-201414458249-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Sep 13, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

An array printed circuit board (PCB) is provided in which a defective single PCB may be easily replaced. A method of replacing a defective single PCB and a method of manufacturing an electronic apparatus are also provided. The array PCB may include a plurality of single PCBs. A rail portion may surround the single PCBs. A plurality of tab route portions connect the single PCBs to the rail portion, each of the tab route portions including at least one pair of via electrodes. A test terminal portion may be formed at one side of the rail portion and may include a plurality of test terminals. The at least one pair of via electrodes may include a first via electrode, arranged adjacent to the rail portion and electrically connected to a corresponding test terminal, and a second via electrode arranged adjacent to and electrically connected to a corresponding single PCB.

First claim

What is claimed is:

1. An array printed circuit board (PCB) comprising:
a plurality of single PCB portions each having an electronic device mounting area formed on an upper surface thereof;
a rail portion surrounding the plurality of single PCB portions;
a plurality of tab route portions connecting the plurality of single PCB portions to the rail portion, each of the plurality of tab route portions comprising at least one pair of via electrodes extending from an upper surface of the each tab route portion toward an inside thereof, wherein the at least one pair of via electrodes comprises a first via electrode arranged adjacent to the rail portion and a second via electrode arranged adjacent to a corresponding single PCB portion;
a test terminal portion formed at one side of the rail portion, the test terminal portion comprising a plurality of test terminals;
a first conductive pattern extending through the rail portion to electrically connect the first via electrode to a corresponding one of the plurality of test terminals; and
a second conductive pattern electrically connected to the second via electrode and extending to a corresponding one of the single PCB portions.

2. The array PCB of claim 1 , wherein the plurality of single PCB portions, the rail portion, and the plurality of tab route portions each comprise a plurality of insulating layers and a plurality of conductive material layers, wherein the plurality of conductive material layers are separated by the plurality of insulating layers, and wherein the first and second conductive patterns comprise at least some of the conductive material layers and are arranged along a same layer interposed between a pair of insulating layers.

3. The array PCB of claim 1 , wherein the first via electrode and the second via electrode extend from an upper surface of a corresponding tab route portion to the first conductive pattern and the second conductive pattern, respectively.

4. The array PCB of claim 1 , wherein the first via electrode and the second via electrode penetrate the first conductive pattern and the second conductive pattern, respectively, from an upper surface of a corresponding tab route portion toward a lower surface of the corresponding tab route portion.

5. The array PCB of claim 1 , wherein the first conductive pattern and the second conductive pattern are connected to each other.

6. The array PCB of claim 1 , wherein the first conductive pattern and the second conductive pattern are spaced apart from each other in a corresponding tab route portion.

7. The array PCB of claim 1 , further comprising a first via pad and a second via pad formed on an upper surface of a corresponding tab route portion and connected to the first via electrode and the second via electrode, respectively.

8. The array PCB of claim 1 , wherein the plurality of single PCB portions, the rail portion, and the plurality of tab route portions each comprise a plurality of insulating layers and a plurality of conductive material layers, said plurality of conductive material layers comprising a plurality of layers that are separated from each other by corresponding ones of the plurality of insulating layers, wherein the first conductive pattern comprises a plurality of first conductive patterns, each of which connects a test terminal of the test terminal portion to a first via electrode of the plurality of tab route portions, and wherein at least some of the plurality of first conductive patterns are conductive material layers comprising at least two layers.

9. An array printed circuit board (PCB) comprising:
a plurality of single PCB portions each having an electronic device mounting area formed on an upper surface thereof;
a rail portion surrounding the plurality of single PCB portions;
a plurality of tab route portions connecting the plurality of single PCB portions to the rail portion, each of the plurality of tab route portions comprising at least one pair of via electrodes extending from an upper surface of the each tab route portion toward an inside thereof; and
a test terminal portion formed at one side of the rail portion, the test terminal portion comprising a plurality of test terminals,
wherein the at least one pair of via electrodes comprises a first via electrode arranged adjacent to the rail portion and electrically connected to a corresponding test terminal, and a second via electrode arranged adjacent to a corresponding single PCB portion and electrically connected to the corresponding single PCB portion.

10. The array PCB of claim 9 , wherein the corresponding test terminal and the first via electrode are connected to each other via a first conductive pattern extending in the array PCB, and wherein the corresponding single PCB portion and the second via electrode are connected to each other via a second conductive pattern extending in the array PCB.

11. The array PCB of claim 10 , wherein the first conductive pattern and the second conductive pattern are formed at the same level from an upper surface of the array PCB.

12. The array PCB of claim 10 , wherein the first conductive pattern is a multi-layered pattern extending in the array PCB.

13. The array PCB of claim 12 , wherein the first conductive pattern comprises at least one via plug that connects patterns of the multi-layered pattern to each other.

14. The array PCB of claim 12 , wherein a pattern of at least one layer from among the multi-layer patterns of the first conductive pattern and the second conductive pattern are formed at the same level from an upper surface of the array PCB.

15. An array printed circuit board (PCB) comprising:
a plurality of single PCB portions;
a rail portion surrounding the plurality of single PCB portions;
a plurality of tab route portions connecting the plurality of single PCB portions to the rail portions;
a pair of via electrodes arranged in one or more of the tab route portions connected to a corresponding one of the single PCB portions, said via electrodes extending from an upper surface of the tab route portion toward an inner portion thereof;
a test terminal portion arranged at one or more sides of the rail portion, the test terminal portion comprising a plurality of test terminals;
a first via electrode from among the pair of via electrodes arranged adjacent to the rail portion and being electrically connected to a corresponding test terminal; and
a second via electrode from among the pair of via electrodes arranged adjacent to and electrically connected to the corresponding single PCB portion.

16. The array PCB of claim 15 further comprising a solder layer electrically connecting the first via electrode to the second via electrode.

Assignees

• Kim Young-Hoon
• Choi Hyun-Seok
• Lee Joo-Han
• Choe Da-Hye
• Samsung Electronics Co Ltd

Inventors

• Kim Young-Hoon
• Choi Hyun-Seok
• Lee Joo-Han
• Choe Da-Hye

Classifications

• H05K3/0097

  Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence) · CPC title

• H05K3/225

  Correcting or repairing of printed circuits (H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence) · CPC title

• H05K1/0268 Primary

  for electrical inspection or testing · CPC title

• H05K3/0052

  Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards · CPC title

• H05K1/0292

  having a modifiable lay-out, i.e. adapted for engineering changes or repair (H05K1/0293 takes precedence) · CPC title