Digital-analog converter and digital-analog conversion device executing digital-analog conversion after delta sigma

Patent metadata

Field	Value
Publication number	US-9450600-B2
Application number	US-201414779064-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 28, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.

First claim

The invention claimed is:

1. A digital-analog converter comprising:
a first analog segment unit including a first sampling switch group and a first sampling capacitor group having a plurality of capacitors, the plurality of capacitors being charged according to a signal level of a first digital signal in a sampling phase;
a second analog segment unit including a second sampling switch group and a second sampling capacitor group having a plurality of capacitors, the plurality of capacitors being charged according to a signal level of a second digital signal in the sampling phase; and
a calculation unit including an operational amplifier and an integration capacitor, the calculation unit outputting an analog signal according to a charged voltage of each capacitor of the first sampling capacitor group or a charged voltage of each capacitor of the second sampling capacitor group in an integral phase, the operational amplifier having a summing node and an output terminal, the integration capacitor being connected between the summing node and the output terminal,
wherein, one analog segment unit of the first and second analog segment units is in the sampling phase and disconnected to the summing node while the other analog segment unit is in the integral phase and connected to the summing node.

2. The digital-analog converter according to claim 1 ,
wherein the first sampling switch group is switched such that the first analog segment unit is connected to an input terminal inputting the first digital signal and a reference voltage in the sampling phase, and the first sampling switch group is switched such that the first analog segment unit is connected to the calculation unit in the integral phase, and
wherein the second sampling switch group is switched such that the second analog segment unit is connected to an input terminal inputting the second digital signal and the reference voltage in the sampling phase, and the second sampling switch group is switched such that the second analog segment unit is connected to the calculation unit in the integral phase.

3. A digital-analog conversion device comprising:
a delta sigma modulator;
a data-weighted-averaging (DWA) processor electrically connected to the delta sigma modulator; and
the digital-analog converter according to claim 1 electrically connected to the DWA processor.

4. A digital-analog conversion device comprising:
a delta sigma modulator;
a two-tap digital FIR filter electrically connected to the delta sigma modulator;
a data-weighted-averaging (DWA) processor electrically connected to the two-tap digital FIR filter; and
the digital-analog converter according to claim 1 electrically connected to the DWA processor.

5. A digital-analog conversion device comprising:
a delta sigma modulator;
a data-weighted-averaging (DWA) processor electrically connected to the delta sigma modulator;
a two-tap analog FIR filter electrically connected to the DWA processor; and
the digital-analog converter according to claim 1 electrically connected to the two-tap analog FIR filter.

6. A digital-analog converter comprising:
three or more analog segment units each including a sampling switch group and a sampling capacitor group having a plurality of capacitors, the three or more analog segment units connected to an input terminal inputting a digital signal and a reference voltage in a sampling phase, the plurality of capacitors being charged according to a signal level of the input digital signal; and
a calculation unit including an operational amplifier and an integration capacitor, in an integral phase, the calculation unit connected to one analog segment unit of the three or more analog segment units, and the calculation unit outputting an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the connected analog segment unit,
wherein the three or more analog segment units sequentially inputs the digital signal, and
wherein, when a first analog segment unit of the three or more analog segment units is in the sampling phase, a second analog segment unit of the three or more analog segment units is in the integral phase, and the other analog segment units of the three or more analog segment units are in an empty phase of not being connected to the reference voltage, the input terminal and the calculation unit.

7. The digital-analog converter according to claim 6 , wherein the each sampling switch group of the three or more analog segment units is switched such that the analog segment unit is connected to the input terminal inputting the digital signal and the reference voltage in the sampling phase, the each sampling switch group is switched such that the analog segment unit is connected to the calculation unit in the integral phase, and the each sampling switch group is switched such that the analog segment unit is not connected to the reference voltage, the input terminal and the calculation unit in the empty phase.

8. A digital-analog conversion device comprising:
a delta sigma modulator;
a data-weighted-averaging (DWA) processor electrically connected to the delta sigma modulator; and
the digital-analog converter according to claim 6 electrically connected to the DWA processor.

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Chubachi Tatsuya
• Nakanishi Junya

Classifications

• H03M1/802

  using capacitors, e.g. neuron-mos transistors, charge coupled devices · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/662 Primary

  Multiplexed conversion systems · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title