Circuits and methods providing three-level signals at a synchronous buck converter

Patent metadata

Field	Value
Publication number	US-9450491-B2
Application number	US-201514630318-A
Country	US
Kind code	B2
Filing date	Feb 24, 2015
Priority date	Oct 23, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

First claim

What is claimed is:

1. A circuit comprising:
a three-level buck converter having:
a plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor;
an inductor configured to receive a voltage from first capacitor and the plurality of input switches;
a second capacitor at an output node of the buck converter; and
a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

2. The circuit of claim 1 , wherein the first capacitor has a substantially same capacitance as the second capacitor.

3. The circuit of claim 1 , wherein the first and second capacitors are each greater than the switched capacitor by at least an order of magnitude as measured in Farads.

4. The circuit of claim 1 , wherein the switched capacitor is disposed between the input node of the inductor and ground.

5. The circuit of claim 1 , further comprising a transistor in communication with the switched capacitor, the transistor configured to open and close a conductive path between the input node of the inductor and ground.

6. The circuit of claim 1 , wherein the three-level buck converter is part of a system on a chip and is configured to power a processing core.

7. The circuit of claim 1 , wherein plurality of input switches are coupled to VDD and ground, further wherein the voltage from the plurality of input switches varies between either zero and VDD/2 or VDD/2 and VDD.

8. The circuit of claim 1 , further comprising:
a switch in communication with the switched capacitor, the switch configured to open and close a conductive path between the input node of the inductor and ground; and
a pulse width modulation controller configured to provide control signals to the plurality of input switches and configured to control the switch in communication with the switched capacitor.

9. The circuit of claim 1 , further comprising a pulse width modulation controller configured to receive an output voltage of the three-level buck converter and to vary a duty cycle of control signals to the input switches in response to receiving the output voltage.

10. A method comprising:
receiving a plurality of pulse width modulated control signals at input switches of a three-level buck converter, the input switches being coupled with a first capacitor and configured to charge and discharge the first capacitor in response to the plurality of pulse width modulated control signals;
producing a voltage at an input node of an inductor of the three-level buck converter, the voltage at the input node of the inductor being controlled by the pulse width modulated control signals, the three-level buck converter further including a second capacitor at an output node of the inductor;
producing an output voltage at an output node of the three-level buck converter in response to the voltage at the input node of the inductor; and
charging and discharging a switched capacitor at the input node of the inductor.

11. The method of claim 10 , further comprising:
opening a switch at the switched capacitor in response to a load.

12. The method of claim 10 , further comprising:
closing a switch at the switched capacitor in response to a load.

13. The method of claim 10 , wherein the first capacitor and the second capacitor have a substantially similar value.

14. The method of claim 10 , wherein the first and second capacitor are larger than the switched capacitor by at least an order of magnitude.

15. The method of claim 10 , wherein discharging the switched capacitor comprises discharging less energy than in a ripple at the voltage at the input node of the inductor.

16. The method of claim 10 , wherein the charging and discharging the switched capacitor comprises reducing a ripple in the voltage at the input node of the inductor.

17. The method of claim 10 , wherein the three-level buck converter includes four input switches, wherein a first set of two of the input switches receives a first one of the pulse width modulated control signals, and wherein a second set of two of the input switches receives a second one of the pulse width modulated control signals, wherein the first and second pulse width modulated control signals are phase shifted by 180°.

18. A circuit comprising:
a three-level buck converter having:
a set of input transistors configured to be controlled by first and second pulse width modulated signals and also configured to charge and discharge a first capacitor that is in communication with the set of input transistors;
an inductor coupled with the set of input transistors and configured to receive a voltage produced by the charging and discharging of the first capacitor;
a second capacitor at an output node of the three-level buck converter and in communication with the inductor; and
a third capacitor disposed at an input node of the inductor, the third capacitor being at least an order of magnitude smaller than both the first capacitor and the second capacitor.

19. The circuit of claim 18 , further comprising:
a pulse width modulation controller in communication with the three-level buck converter and configured to provide the first and second pulse width modulated signals in response to a reference signal and a feedback signal from the output node of the three-level buck converter.

20. The circuit of claim 18 , further comprising:
a transistor configured to open and close a conductive path to ground, the conductive path including the third capacitor.

21. The circuit of claim 18 , wherein the first and second capacitors have a substantially same value as measured in Farads.

22. The circuit of claim 18 , wherein the set of input transistors comprises four transistors disposed between VDD and ground.

23. The circuit of claim 18 , wherein the set of input transistors comprises four transistors disposed between VDD and ground, further wherein the first capacitor is coupled to ground when a first one of the transistors is on and is coupled to VDD when a second one of the transistors is on.

24. The circuit of claim 18 , wherein the set of input transistors comprises two p-type transistors and two n-type transistors disposed between VDD and ground.

25. The circuit of claim 18 , wherein the set of input transistors comprises two p-type transistors and two n-type transistors disposed between VDD and ground, further wherein the first capacitor is coupled to a node between a first n-type transistor and a second n-type transistor and coupled to another node between a first p-type transistor and a second p-type transistor.

26. The circuit of claim 18 , further comprising:
a processing core receiving an output voltage of the three-level buck controller.

27. The circuit of claim 18 , further comprising:
the feedback loop including a pulse width modulation controller configured to provide the first and second pulse width modulated signals to maintain an output voltage of the three-level buck converter at a desired level.

28. A three-level buck converter comprising:
means for receiving first and second pulse width modulated signals and charging and discharging a first capacitor between a voltage rail and ground in response to the first and second pulse width modulated signals;
means for generating an output voltage of the th

Assignees

• Qualcomm Inc

Inventors

• Zhang Chuang
• Doyle James Thomas
• Mahmoudi Farsheed
• Shayan Arani Amirali

Classifications

• H02M7/483

  Converters with outputs that each can have more than two voltages levels · CPC title

• H02M2003/072

  Electricity · mapped topic

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M7/4837

  Flying capacitor converters · CPC title

• H02M3/072

  adapted to generate an output voltage whose value is lower than the input voltage · CPC title