Thin film transistor, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-9450101-B2
Application number	US-201314136994-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 25, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A thin film transistor, comprising: a substrate; a first electrode formed on the substrate; a first insulation layer formed on the first electrode; a gate electrode formed on the first insulation layer; a second insulation layer formed on the gate electrode; an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and a second electrode formed on the active layer and electrically connected to the first electrode through the active layer, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a substrate;
a first electrode formed on the substrate;
a first insulation layer formed on the first electrode;
a gate electrode formed on the first insulation layer;
a second insulation layer formed on the gate electrode;
an active layer formed in a hole penetrating through the first and second insulation layers, wherein the active layer is filled in the whole hole, the hole does not run through the gate electrode and is physically isolated from the gate electrode, so that the active layer is electrically isolated from the gate electrode; and
a second electrode formed on the active layer and electrically connected to the first electrode through the active layer,
wherein the first electrode is used as one of a source electrode and a drain electrode, and the second electrode is used as the other of the source electrode and the drain electrode.

2. The thin film transistor according to claim 1 ,
wherein the gate electrode is located between the first electrode and the second electrode.

3. The thin film transistor according to claim 2 ,
wherein the gate electrode is located between the first insulation layer and the second insulation layer.

4. The thin film transistor according to claim 1 ,
wherein the active layer is formed to extend upward beyond a top surface of the second insulation layer.

5. The thin film transistor according to claim 1 ,
wherein the active layer is made of oxide semiconductor material, and the first and second insulation layers are made of inorganic insulation material.

6. The thin film transistor according to claim 2 ,
wherein the first insulation layer or the second insulation layer has a thickness of 50 nm˜500 nm.

7. The thin film transistor according to claim 1 ,
wherein the active layer is made of amorphous silicon, polycrystalline silicon or microcrystalline silicon, and the first and second insulation layers are made of organic insulation material.

8. The thin film transistor according to claim 7 ,
wherein the first insulation layer or the second insulation layer has a thickness of 0.5 μm˜2.5 μm.

9. The thin film transistor according to claim 1 ,
wherein the gate electrode has a thickness of 10 nm˜2000 nm.

10. An array substrate comprising a thin film transistor according to claim 1 , the thin film transistor comprising:
a substrate;
a first electrode formed on the substrate;
a first insulation layer formed on the first electrode;
a gate electrode formed on the first insulation layer;
a second insulation layer formed on the gate electrode;
an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and
a second electrode formed on the active layer and electrically connected to the first electrode through the active layer,
wherein the first electrode is used as one of a source electrode and a drain electrode, and the second electrode is used as the other of the source electrode and the drain electrode.

11. The array substrate according to claim 10 , further comprising:
a pixel electrode formed on the second electrode and electrically connected to the second electrode.

12. The array substrate according to claim 10 , further comprising:
a passivation layer formed between the second electrode and the pixel electrode and having a via through which the pixel electrode is electrically connected to the second electrode.

13. A display apparatus comprising an array substrate according to claim 10 , the array substrate comprising a thin film transistor, the thin film transistor comprising:
a first electrode formed on the substrate;
a first insulation layer formed on the first electrode;
a gate electrode formed on the first insulation layer;
a second insulation layer formed on the gate electrode;
an active layer penetrating through the first and second insulation layers and electrically isolated from the gate electrode; and
a second electrode formed on the active layer and electrically connected to the first electrode through the active layer,
wherein the first electrode is used as one of a source electrode and a drain electrode, and the second electrode is used as the other of the source electrode and the drain electrode.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yuan Guangcai

Classifications

• H10D30/6728 Primary

  Vertical TFTs · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6746

  Amorphous silicon · CPC title