Semiconductor memory device having an electrically floating body transistor

Patent metadata

Field	Value
Publication number	US-9450090-B2
Application number	US-201514930049-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Oct 4, 2010
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

First claim

What is claimed is:

1. An integrated circuit comprising:
an array of memory cells formed in a semiconductor, the array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising:
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; and
a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and

control circuitry configured to provide electrical signals to said buried region.

2. The integrated circuit of claim 1 , wherein said memory cell further comprises a bit line region on said surface, the bit line region having the second conductivity type.

3. The integrated circuit of claim 2 , further comprising second control circuitry configured to provide electrical signals to said bit line region.

4. The integrated circuit of claim 1 , wherein said electrical signals to said buried region have an amplitude or polarity dependent on an operation of said array of memory cells.

5. The integrated circuit of claim 1 , wherein said control circuitry comprises a voltage generator circuit.

6. The integrated circuit of claim 5 , further comprising a multiplexer electrically connected between said voltage generator circuit and said buried region, said multiplexer configured to apply periodic pulses of positive voltage to said buried region.

7. The integrated circuit of claim 1 , wherein said control circuitry comprises a reference generator circuit configured to sense potential of said floating body region.

8. The integrated circuit of claim 3 , wherein said second control circuitry comprises a read circuit connected to said bit line region and configured to read a state of said memory cell.

9. The integrated circuit of claim 8 , further comprising a reference generator circuit connected to said read circuit.

10. An integrated circuit comprising:
an array of memory cells formed in a semiconductor, the array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and a plurality of columns, wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each semiconductor memory cell of the plurality of semiconductor memory cells comprising:
a bipolar device having a floating base region, a first region, a second region, and a gate region wherein:
a state of said semiconductor memory cell is stored in said floating base region, said floating base region having a surface,
said first region is located at the surface of said floating base region,
said second region is located below said floating base region,
said second region is commonly connected to at least two of said semiconductor memory cells in said matrix, and
said gate region overlays two of said semiconductor memory cells along the column direction, and

control circuitry configured to provide electrical signals to said second region.

11. The integrated circuit of claim 10 , further comprising a plurality of source lines crossing the array in the first direction beneath one or more surfaces of said plurality of semiconductor memory cells, wherein the plurality of source lines are coupled to one or more second regions of said plurality of semiconductor memory cells.

12. The integrated circuit of claim 11 , further comprising a plurality of bit lines crossing the array in the second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled to one or more said first regions.

13. The integrated circuit of claim 10 , further comprising a plurality of word lines crossing the array in the first direction above one or more surfaces, wherein the plurality of word lines are coupled to one or more gate regions.

14. The integrated circuit of claim 10 , further comprising second control circuitry configured to provide electrical signals to said first region.

15. The integrated circuit of claim 10 , wherein said electrical signals to said second region have an amplitude or polarity dependent on an operation of said array of memory cells.

16. The integrated circuit of claim 10 , wherein said control circuitry comprises a voltage generator circuit.

17. The integrated circuit of claim 16 , further comprising a multiplexer electrically connected between said voltage generator circuit and said second region, said multiplexer configured to apply periodic pulses of positive voltage to said second region.

18. The integrated circuit of claim 10 , wherein said control circuitry comprises a reference generator circuit configured to sense potential of said floating base region.

19. The integrated circuit of claim 14 , wherein said second control circuitry comprises a read circuit connected to said first region and configured to read a state of said semiconductor memory cell.

20. The integrated circuit of claim 19 , further comprising a reference generator circuit connected to said read circuit.

Assignees

• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto
• Or-Bach Zvi

Classifications

• G11C11/4026

  using bipolar transistors · CPC title

• G11C11/39

  using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT} · CPC title

• G11C14/0018

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G11C2211/4016

  Memory devices with silicon-on-insulator cells · CPC title

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title