Lateral super junctions with high substrate breakdown and build in avalanche clamp diode

Patent metadata

Field	Value
Publication number	US-9450050-B2
Application number	US-201314062868-A
Country	US
Kind code	B2
Filing date	Oct 24, 2013
Priority date	Nov 30, 2009
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

First claim

We claim:

1. A semiconductor power device comprising:
a semiconductor substrate comprising a super-junction structure including a plurality of alternating P-doped and N-doped layers extending laterally from a source column to a drain column wherein said source column and drain column extend downward in said semiconductor substrate through two opposite sides of said super-junction structure disposed in said semiconductor substrate;
a gate column for applying a voltage thereon to control a current transmitted laterally through said super-junction structure between said source and said drain columns; wherein the semiconductor substrate is a P substrate and wherein the drain column is an N+ column to form a Zener diode at a junction of said drain column with said P substrate to function as a built-in avalanche clamp diode;
source and drain graded N diffusion regions surrounding sidewalls of said source and drain columns respectively; and
said gate column further comprises a trench P+ column connected to said P doped layers of said super-junction structure and disposed near said source column outside of an area between said source column and said drain column wherein said source column is segmented to have a gap area for said P+ gate column to apply a voltage to control a current transmitted through said super junction structure.

2. The semiconductor power device of claim 1 further comprising:
a buried doped region disposed in said semiconductor substrate below the drain column which increases the effective radius of a bottom of the drain column for suppressing an electrical field crowding.

3. The semiconductor power device of claim 2 wherein:
the buried doped region is an N-buffer layer extending laterally from and vertically disposed below said drain column.

4. The semiconductor power device of claim 3 wherein:
the buried doped region comprising an N-buffer layer extending to an area near the drain column.

5. The semiconductor power device of claim 2 wherein:
the buried doped region is an N-buffer region disposed in said semiconductor substrate below and surrounding bottom sidewalls and a bottom wall of the drain column.

6. The semiconductor power device of claim 1 wherein:
said trench P+ column is connected to said P doped P-doped layers of said super-junction structure is connected to the P substrate.

7. The semiconductor power device of claim 1 further comprising:
a conductive field plate disposed on a top surface of said drain N+ column.

8. The semiconductor power device of claim 1 further comprising:
an active area for disposing said super-junction structure extends between said source and drain column; and
a termination area outside said active area comprises a P+ termination column extending down to the P substrate, the P+ termination column being located between the active area and a semiconductor die edge.

9. The semiconductor power device of claim 1 further comprising:
a graded P diffusion region having a graded P dopant profile diffused from said trench P+ column of said gate column.

10. The semiconductor power device of claim 1 further comprising:
a gate electrode comprising a gate metal layer disposed below a bottom surface of said semiconductor substrate.

11. The semiconductor power device of claim 1 wherein:
said trench P+ gate column extends into said P substrate at a greater depth in said semiconductor substrate than said source and drain columns.

12. A semiconductor power device comprising:
a semiconductor substrate comprising a super-junction structure including a plurality of alternating P-doped and N-doped layers extending laterally from a source column to a drain column wherein said source column and drain column extend downward in said semiconductor substrate through two opposite sides of said super-junction structure disposed in said semiconductor substrate;
a gate column for applying a voltage thereon to control a current transmitted laterally through said super-junction structure between said source and said drain columns; wherein the semiconductor substrate is a P substrate and wherein the drain column is an N+ column to form a Zener diode at a junction of said drain column with said P substrate to function as a built-in avalanche clamp diode;
a source and drain graded N diffusion regions surrounding sidewalls of said source and drain columns respectively;
said gate column further comprises a P+ column disposed in said gate column connected to said P-doped layers of said super-junction structure for applying a voltage to control a current transmitted through said super junction structure; and
a gate electrode comprising a gate metal layer disposed below a bottom surface of said semiconductor substrate.

13. The semiconductor power device of claim 12 further comprising:
a graded P diffusion region having a graded P dopant profile diffused from said P+ column of said gate column.

14. The semiconductor power device of claim 12 wherein:
said P+ column extends into said P substrate at a greater depth in said semiconductor substrate than said source and drain columns.

15. The semiconductor power device of claim 12 further comprising:
wherein the source, drain and gate columns in the super-junction structure form a JFET, the semiconductor power device further comprising
a MOSFET connected in a cascode circuit configuration with said JFET.

16. The semiconductor power device of claim 12 further comprising:
source/gate fingers having the source and gate columns staggered along a length of the source/gate fingers; and
drain fingers having the drain column running along the length of the drain finger; wherein the source/gate fingers are interdigitated with the drain fingers.

17. The semiconductor power device of claim 16 wherein:
the semiconductor surface in a vicinity to tips of the source/gate fingers and drain fingers are implanted with the same conductivity type as the respective column located at the tips of the respective fingers.

18. The semiconductor power device of claim 12 further comprising:
a buried doped region disposed in said semiconductor substrate below the drain column which increases the effective radius of a bottom of the drain column for suppressing an electrical field crowding.

19. The semiconductor power device of claim 18 wherein:
the buried doped region is an N-buffer layer extending laterally from and vertically disposed below said drain column.

20. The semiconductor power device of claim 19 wherein:
the buried doped region comprising an N-buffer layer extending to an area near the drain column.

21. The semiconductor power device of claim 12 wherein:
said P+ column is connected to said P-doped layers of said super-junction structure and is connected to the P substrate.

Assignees

• Bobde Madhur
• Bhalla Anup
• Yilmaz Hamza
• Ma Wilson
• Guan Lingping
• Lee Yeeheng
• Chen John
• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Bhalla Anup
• Yilmaz Hamza
• Ma Wilson
• Guan Lingping
• Lee Yeeheng
• Chen John

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title