Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9450049-B2
Application number	US-201414276421-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	Jun 24, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first region and a second region;
a silicon-germanium layer on the substrate;
a first semiconductor pattern on the silicon-germanium layer of the first region, the first semiconductor pattern including an element semiconductor;
a second semiconductor pattern on the silicon-germanium layer of the second region, the second semiconductor pattern including a Group III-V semiconductor material, and
a germanium buffer pattern between the second semiconductor pattern and the silicon-germanium layer of the second region, wherein the first semiconductor pattern includes germanium, wherein a bottom surface of the first semiconductor pattern and a bottom surface of the germanium buffer pattern are on a top surface of the silicon-germanium layer, and wherein a height from a top surface of the substrate to a top surface of the first semiconductor pattern is greater than a height from the top surface of the substrate to a top surface of the germanium buffer pattern.

2. The semiconductor device as claimed in claim 1 , further comprising: a buffer pattern between the silicon-germanium layer and the germanium buffer pattern, wherein the buffer pattern includes a Group III-V semiconductor material.

3. The semiconductor device as claimed in claim 1 , further comprising:
a capping pattern on the second semiconductor pattern.

4. The semiconductor device as claimed in claim 3 , wherein the capping pattern includes a Group III-V semiconductor material.

5. The semiconductor device as claimed in claim 3 , wherein:
the capping pattern includes a first energy band gap, and
the second semiconductor pattern includes a second energy band gap which is less than the first energy band gap.

6. The semiconductor device as claimed in claim 1 , further comprising: a first insertion pattern between the first semiconductor pattern and the silicon-germanium layer.

7. The semiconductor device as claimed in claim 6 , further comprising:
a second insertion pattern between the germanium buffer pattern and the second semiconductor pattern, wherein the first insertion pattern and the second insertion pattern are at a same level.

8. The semiconductor device as claimed in claim 1 , further comprising:
an insertion layer on the silicon-germanium layer,
wherein the first semiconductor pattern and the second semiconductor pattern are on the insertion layer.

9. The semiconductor device as claimed in claim 1 , wherein:
the substrate is a silicon substrate.

10. A semiconductor device, comprising:
a silicon substrate including a first region and a second region;
a silicon-germanium layer on the silicon substrate;
a first transistor on the silicon-germanium layer in the first region; and
a second transistor on the silicon-germanium layer in the second region, wherein the first transistor includes a germanium channel layer on the silicon-germanium layer and a first gate electrode on and crossing the germanium channel layer, wherein the second transistor includes a first buffer pattern including germanium on the silicon-germanium layer, a Group III-V semiconductor channel layer including a first Group III-V semiconductor material on the first buffer pattern, and a second gate electrode crossing the Group III-V semiconductor channel layer on the Group III-V semiconductor channel layer, and wherein a height from a top surface of the silicon substrate to a top surface of the germanium channel layer is greater than a height from the top surface of the silicon substrate to a top surface of the first buffer pattern.

11. The semiconductor device as claimed in claim 10 , wherein:
the first transistor includes a first insertion pattern between the germanium channel layer and the silicon-germanium layer,
the second transistor includes a second insertion pattern between the first buffer pattern and the Group III-V semiconductor channel layer, and
the first insertion pattern and the second insertion pattern are at a same level.

12. The semiconductor device as claimed in claim 10 , further comprising:
a second buffer pattern between the Group III-V semiconductor channel layer and the first buffer pattern, wherein the second buffer pattern includes a second Group III-V semiconductor material having an energy band gap greater than an energy band gap of the first Group III-V semiconductor material.

13. The semiconductor device as claimed in claim 10 , further comprising:
a capping pattern between the Group III-V semiconductor channel layer and the second gate electrode, wherein the capping pattern includes a third Group III-V semiconductor material having an energy band gap greater than an energy band gap of the first Group III-V semiconductor.

Assignees

• Kwon Tae-Yong
• Kim Sang-Su
• Yang Jung-Gil
• Choi Jung-Dal
• Samsung Electronics Co Ltd

Inventors

• Kwon Tae-Yong
• Kim Sang-Su
• Yang Jung-Gil
• Choi Jung-Dal

Classifications

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D12/021

  of gated diodes, e.g. field-controlled diodes [FCD] · CPC title

• H10D62/85 Primary

  being Group III-V materials, e.g. GaAs · CPC title

• H10D86/215

  comprising FinFETs · CPC title