Semiconductor structure with fin structure and wire structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9450046-B2
Application number	US-201514592089-A
Country	US
Kind code	B2
Filing date	Jan 8, 2015
Priority date	Jan 8, 2015
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes a first wire structure formed over the fin structure and a source structure and a drain structure formed at two opposite sides of the fin structure. The semiconductor structure further includes a gate structure formed over the fin structure. In addition, the fin structure and the first wire structure are separated by the gate structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a first fin structure formed over the substrate;
at least one first wire structure formed over the first fin structure;
a source structure and a drain structure formed at two opposite sides of the first fin structure; and
a second fin structure formed over the substrate;
at least one second wire structure formed over the second fin structure; and
a gate structure formed over the first fin structure and the second fin structure,
wherein a number of the first wire structure formed over the first fin structure is different from a number of the second wire structure formed over the second fin structure.

2. The semiconductor structure as claimed in claim 1 , wherein the first wire structure is surrounded by the gate structure.

3. The semiconductor structure as claimed in claim 1 , wherein the first wire structure is connected with the source structure and the drain structure.

4. The semiconductor structure as claimed in claim 1 , wherein the first fin structure has a first channel height and the first wire structure has a second channel height, and a ratio of the first channel height to the second channel height is in a range from about 1:1 to about 1:0.5.

5. The semiconductor structure as claimed in claim 1 , wherein two first wire structures are formed over the first fin structure, but only one second wire structure is formed over the second fin structure.

6. The semiconductor structure as claimed in claim 5 , wherein the second wire structure formed over the second fin structure is substantially level with one of the first wire structure.

7. The semiconductor structure as claimed in claim 5 , wherein the first fin structure has a first channel height and one of the first wire structure has a third channel height, and a ratio of the first channel height to the third channel height is in a range from about 1:1 to about 1:0.5.

8. The semiconductor structure as claimed in claim 5 , wherein one of the first wire structure has a second channel height and another one of the first wire structure has a third channel height, and the second channel height is different from the third channel height.

9. A method for manufacturing a semiconductor structure, comprising:
forming a first dummy layer over a substrate;
forming a first silicon layer over the first dummy layer;
patterning the first silicon layer, the first dummy layer, and the substrate to form a fin structure, a first dummy structure over the fin structure, and a first wire structure over the first dummy structure;
forming a dummy gate structure across the first wire structure;
forming a source structure and a drain structure at two opposite sides of the fin structure;
removing the dummy gate structure;
removing the first dummy structure; and
forming a gate structure over the fin structure and surrounding the first wire structure.

10. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the first wire structure is connected with the source structure and the drain structure.

11. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the fin structure has a first channel height and the first wire structure has a second channel height no greater than the first channel height.

12. The method for manufacturing a semiconductor structure as claimed in claim 11 , wherein a ratio of the first channel height to the second channel height is in a range from about 1:1 to about 1:0.5.

13. The method for manufacturing a semiconductor structure as claimed in claim 9 , further comprising:
forming a second dummy layer over the first silicon layer;
forming a second silicon layer over the second dummy layer;
patterning the second silicon layer and the second dummy layer to form a second dummy structure over the first wire structure and a second wire structure over the second dummy structure; and
removing the second dummy structure,
wherein the second wire structure is surrounded by the gate structure.

14. The method for manufacturing a semiconductor structure as claimed in claim 13 , further comprising:
forming a masking structure to cover the fin structure and the first wire structure and to expose the second wire structure;
removing the second wire structure; and
removing the masking structure.

15. A method for manufacturing a semiconductor structure, comprising:
forming a first dummy layer over a substrate;
forming a first silicon layer over the first dummy layer;
patterning the first silicon layer, the first dummy layer, and the substrate to form a first fin structure, a first dummy structure over the first fin structure, and a first wire structure over the first dummy structure;
forming a dummy gate structure across the first wire structure;
removing the dummy gate structure;
removing the first dummy structure; and
forming a gate structure across the first wire structure.

16. The method for manufacturing a semiconductor structure as claimed in claim 15 , further comprising:
patterning the first silicon layer, the first dummy layer, and the substrate to form a second fin structure, a second dummy structure over the second fin structure, and a second wire structure over the second dummy structure.

17. The method for manufacturing a semiconductor structure as claimed in claim 16 , further comprising:
forming the dummy gate structure across the second wire structure;
removing the dummy gate structure;
removing the second dummy structure; and
forming the gate structure across the second fin structure.

18. The method for manufacturing a semiconductor structure as claimed in claim 17 , further comprising:
removing the second wire structure.

19. The method for manufacturing a semiconductor structure as claimed in claim 17 , further comprising:
forming a masking structure to cover the first fin structure, the first wire structure, and the second fin structure and to expose the second wire structure;
removing the second wire structure; and
removing the masking structure.

20. The method for manufacturing a semiconductor structure as claimed in claim 15 , further comprising:
removing the first wire structure before the gate structure is formed.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wen Tsung-Yao
• Yeong Sai-Hooi
• Lai Bo-Yu
• Wang Sheng-Chen

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title