Thin film transistor and display device

US9449990B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9449990-B2
Application numberUS-201314423838-A
CountryUS
Kind codeB2
Filing dateAug 30, 2013
Priority dateAug 31, 2012
Publication dateSep 20, 2016
Grant dateSep 20, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.

First claim

Opening claim text (preview).

The invention claimed is: 1. A thin film transistor, comprising: a gate electrode; an oxide semiconductor layer comprising a single layer as a channel layer; an etch stopper layer that protects a surface of the oxide semiconductor layer; a source-drain electrode; and a gate insulator layer arranged between the gate electrode and the channel layer, wherein the oxide semiconductor layer comprises In, Zn and Sn, wherein a hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is from 0.667 to 4 atomic %, wherein the gate insulating layer in direct contact with the oxide semiconductor layer is a silicon oxide film, and wherein the gate insulator layer comprises the single layer structure. 2. The thin film transistor according to claim 1 , wherein when contents (atomic %) of the respective metal elements with respect to all of metal elements excluding oxygen contained in the oxide semiconductor layer are defined as [In], [Zn] and [Sn], respectively, a relationship of 15≦[In]≦35,50≦[Zn]≦60 and 15≦[Sn]≦30 is satisfied. 3. A display device comprising the thin film transistor according to claim 1 . 4. A display device comprising the thin film transistor according to claim 2 . 5. The thin film transistor according to claim 1 , wherein the oxide semiconductor layer comprises from 15 to 20 atomic % of In. 6. The thin film transistor according to claim 1 , wherein the oxide semiconductor layer comprises from 20 to 30 atomic % of Sn.

Assignees

Inventors

Classifications

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

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What does patent US9449990B2 cover?
Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a …
Who is the assignee on this patent?
Kobe Steel Ltd, Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6704. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).