Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure

Patent metadata

Field	Value
Publication number	US-9449980-B2
Application number	US-201414529942-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage during states without electrical bias between a semiconductor channel and charge storage elements. The tunneling dielectric includes a layered stack including at least, from outside to inside, a dielectric metal oxide layer and a silicon oxide layer. Upon application of electrical bias for programming or erasing, the band gap structure of the tunneling dielectric provides a lower tunneling barrier than an ONO stack of a comparable effective oxide thickness. Additionally, due to higher capacitive coupling to the channel with high-k metal oxide layer(s) in the tunneling dielectric, the efficiency of program, erase and read operations can be improved. During a zero-bias state, the tunneling dielectric can provide a higher energy barrier than the ONO stack, thereby providing enhanced data retention than the ONO stack.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a stack including an alternating plurality of electrically insulating layers and electrically conductive layers located over a substrate;
a memory opening extending through the stack;
a memory film located at a periphery of the memory opening; and
a semiconductor channel contacting an inner sidewall of the memory film, wherein:
the memory film comprises, from outside to inside, at least one charge storage element, and a tunneling dielectric contacting the semiconductor channel;
the tunneling dielectric comprises a layered stack including at least, from outside to inside, a dielectric metal oxide layer having a dielectric constant greater than 7.9 and a silicon oxide layer; and
the tunneling dielectric further comprises an element selected from:
a silicon nitride layer in contact with an inner sidewall of the dielectric metal oxide layer and an outer sidewall of the silicon oxide layer; or
an additional dielectric metal oxide layer in contact with an inner sidewall of the dielectric metal oxide layer and an outer sidewall of the silicon oxide layer.

2. The monolithic three-dimensional memory device of claim 1 , wherein the dielectric metal oxide layer comprises an oxide of at least one metal selected from Al, transition metal elements, Lanthanides, and Actinides.

3. The monolithic three-dimensional memory device of claim 2 , wherein the oxide of the at least one metal consists essentially of the at least one metal and oxygen, or of the at least one metal, oxygen, and nitrogen.

4. The monolithic three-dimensional memory device of claim 1 , wherein an interface between the dielectric metal oxide layer and the silicon oxide layer extends through the stack.

5. The monolithic three-dimensional memory device of claim 1 , wherein the silicon oxide layer is in contact with an inner sidewall of the dielectric metal oxide layer.

6. The monolithic three-dimensional memory device of claim 5 , wherein the dielectric metal oxide layer is in contact with an inner sidewall of the at least one charge storage element.

7. The monolithic three-dimensional memory device of claim 6 , wherein the tunneling dielectric further comprises another dielectric metal oxide layer in contact with an inner sidewall of the silicon oxide layer and an outer sidewall of the semiconductor channel.

8. The monolithic three-dimensional memory device of claim 6 , wherein the silicon oxide layer is in contact with a sidewall of the semiconductor channel.

9. The monolithic three-dimensional memory device of claim 5 , wherein the tunneling dielectric further comprises another silicon oxide layer in contact with an outer sidewall of the dielectric metal oxide layer and with an inner sidewall of the at least one charge storage element.

10. The monolithic three-dimensional memory device of claim 1 , wherein the tunneling dielectric further comprises the silicon nitride layer in contact with the inner sidewall of the dielectric metal oxide layer and the outer sidewall of the silicon oxide layer.

11. The monolithic three-dimensional memory device of claim 1 , wherein the tunneling dielectric further comprises the additional dielectric metal oxide layer in contact with the inner sidewall of the dielectric metal oxide layer and the outer sidewall of the silicon oxide layer.

12. The monolithic three-dimensional memory device of claim 1 , wherein the at least one charge storage element is selected from a charge trapping layer and a set of at least one floating gate.

13. The monolithic three-dimensional memory device of claim 1 , wherein the at least one charge storage element comprises silicon nitride in contact with an outer sidewall of the tunneling dielectric and with an inner sidewall of a blocking dielectric.

14. The monolithic three-dimensional memory device of claim 1 , further comprising a blocking dielectric in contact with the at least one charge storage element, wherein the blocking dielectric comprises a stack, from outside to inside, another dielectric metal oxide layer and another silicon oxide layer, wherein an effective oxide thickness of the blocking dielectric is greater than an effective oxide thickness of the tunneling dielectric.

15. The monolithic three-dimensional memory device of claim 1 , wherein the silicon oxide layer has a thickness in a range from 0.5 nm to 5 nm, and the dielectric metal oxide layer has a thickness in a range from 0.5 nm to 5 nm.

16. The monolithic three-dimensional memory device of claim 1 , wherein:
the device comprises a vertical NAND device located in a device region; and
at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

17. A method of manufacturing a monolithic three-dimensional memory device, comprising:
forming a stack of alternating plurality of first material layers and second material layers over a substrate;
forming a memory opening through the stack;
forming at a periphery of the memory opening from outside to inside, at least one charge storage element and a tunneling dielectric, the tunneling dielectric including a dielectric metal oxide layer having a dielectric constant greater than 7.9 and a silicon oxide layer;
forming an element selected from a silicon nitride layer and an additional dielectric metal oxide layer on an inner sidewall of the dielectric metal oxide layer, wherein the silicon oxide layer is formed on the selected element; and
forming a semiconductor channel over an inner sidewall of the tunneling dielectric.

18. The method of claim 17 , wherein forming the dielectric metal oxide layer comprises depositing an oxide of at least one metal selected from Al, transition metal elements, Lanthanides, and Actinides.

19. The method of claim 18 , wherein the oxide of the at least one metal consists essentially of the at least one metal and oxygen, or of the at least one metal, oxygen, and nitrogen.

20. The method of claim 17 , wherein the silicon oxide layer is formed directly on an inner sidewall of the dielectric metal oxide layer.

21. The method of claim 20 , wherein the dielectric metal oxide layer is formed directly on an inner sidewall of the at least one charge storage element.

22. The method of claim 21 , further comprising forming an additional dielectric metal oxide layer directly on an inner sidewall of the silicon oxide layer, wherein

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Rabkin Peter

Classifications

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title