Semiconductor devices and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9449977-B2
Application number	US-201414570365-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Mar 14, 2011
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate, the storage nodes each having a height in the vertical direction between a bottom and a top of the storage node;
a lower support pattern in contact with the storage nodes between the bottom and the top of the plurality of storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction;
an upper support pattern in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction;
wherein the lower support pattern is positioned at a position in the vertical direction that is greater than or equal to a half of the height of the storage nodes, wherein the lower support pattern has the substantially same shape as the upper support pattern in plan view;
wherein the lower support pattern has a first maximum thickness in the vertical direction; and
wherein the upper support pattern has a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern, and wherein the upper support pattern has a lower surface that is substantially flat and an upper surface that is substantially wavy.

2. The semiconductor device of claim 1 , wherein the lower surface of the upper support pattern faces the lower support pattern and wherein the upper surface of the upper support pattern is opposite the lower surface.

3. A semiconductor device, comprising:
a substrate;
a plurality of storage nodes extending in a vertical direction relative to the substrate;
a lower support pattern in contact with the storage nodes between a bottom and a top of the plurality of storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction; the lower support pattern having a first vertical cross-sectional profile; and
an upper support pattern in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, the upper support pattern having a second vertical cross-sectional profile, wherein the second vertical cross-sectional profile is different than the first vertical cross-sectional profile,
wherein the upper support pattern has a lower surface facing the lower support pattern and an upper surface opposite the lower surface, and
wherein the lower surface is substantially flat and the upper surface is substantially wavy such that the upper support pattern has a thickness that varies substantially in the vertical direction.

4. The semiconductor device of claim 3 wherein the lower support pattern has a thickness that is substantially constant.

5. The semiconductor device of claim 3 wherein a portion of the upper support pattern extending between neighboring storage nodes has an intermediate region of relatively greater thickness than first and second end regions thereof.

6. The semiconductor device of claim 5 wherein the end regions correspond to contact portions of the upper support pattern at which the upper support pattern makes contact with the storage nodes and wherein the intermediate region corresponds to intermediate portions of the upper support pattern between neighboring storage nodes.

7. A semiconductor device comprising:
a substrate;
an array of storage nodes extending in a vertical direction relative to the substrate, the storage nodes being arranged in rows and columns;
a lower support pattern in contact with the storage nodes between a bottom and a top of the plurality of the storage nodes, the lower support pattern spaced apart from the substrate; the lower support pattern having a plurality of openings, each opening extending between multiple pairs of neighboring storage nodes of the array of storage nodes, wherein multiple openings are present between neighboring rows of the array of storage nodes and wherein multiple openings are present between neighboring columns of the array of storage nodes; and
an upper support pattern in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, the upper support pattern having a plurality of openings, each opening extending between multiple pairs of neighboring storage nodes of the array of storage nodes, wherein multiple openings are present between neighboring rows of the array of storage nodes and wherein multiple openings are present between neighboring columns of the array of storage nodes,
wherein the openings of the lower support pattern and the openings of the upper support pattern correspond with each other in the vertical direction,
wherein the upper support pattern has a lower surface facing the lower support pattern and an upper surface opposite the lower surface, and
wherein the lower surface is substantially flat and the upper surface is substantially wavy such that the upper support pattern has a thickness that varies substantially in the vertical direction.

8. The semiconductor device of claim 7 wherein the openings of the lower support pattern each expose multiple storage nodes of the array of storage nodes, and wherein the openings of the upper support pattern each expose multiple storage nodes of the array of storage nodes.

9. The semiconductor device of claim 3 wherein the lower support pattern has a first maximum thickness in the vertical direction; and wherein the upper support pattern has a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Jungwoo

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L28/60

  Electricity · mapped topic

• H01L27/10852

  Electricity · mapped topic