Electronic component package and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9449944-B2
Application number	US-201314422615-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 21, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.

First claim

The invention claimed is:

1. An electronic component package, comprising:
a sealing resin layer;
first and second electronic components buried in the sealing resin layer, an electrode of each of the first and second electronic components being flush with a surface of the sealing resin layer; and
metal plating pattern layers “A” and “B”, the metal plating pattern layer “A” being in connection with the electrode of the first electronic component, the metal plating pattern layer “B” being in connection with the electrode of the second electronic component,
wherein a part of the surface of the sealing resin layer is provided as an indent surface portion forming a stepped portion that provides different plane levels between the first and second electronic components, and the electrode of either one of the first and second electronic components is flush with the indent surface portion, and thereby the electrode of the first electronic component and the electrode of the second electronic component are on the different plane levels from each other, and
wherein each of the metal plating pattern layers “A” and “B” has a layered structure of a wet plating layer and a dry plating layer, the wet plating layer being located relatively outside, the dry plating layer being located relatively inside.

2. The electronic component package according to claim 1 , wherein a thickness of the metal plating pattern layer “A” and a thickness of the metal plating pattern layer “B” differ from each other.

3. The electronic component package according to claim 1 , wherein an outside surface of the wet plating layer of the metal plating pattern layer “A” is on the same plane level as an outside surface of the wet plating layer of the metal plating pattern layer “B”.

4. The electronic component package according to claim 3 , wherein a thickness of the metal plating pattern layer “A” and a thickness of the metal plating pattern layer “B” differ from each other, and
wherein a difference in thickness between the metal plating pattern layers “A” and “B” is in the range of 2 μm to 100 μm.

5. The electronic component package according to claim 1 , wherein the metal plating pattern layer “A” comprises a further metal plating pattern layer “A′”, and the metal plating pattern layer “B” comprises a further metal plating pattern layer “B′”, the further metal plating pattern layer “A′” being in contact with a sealing resin layer's surface which is flush with the electrode of the first electronic component, the further metal plating pattern layer “B′” being in contact with a sealing resin layer's surface which is flush with the electrode of the second electronic component, and
wherein a thickness of the further metal plating pattern layer “A′” is different from that of the metal plating pattern layer “A”, and a thickness of the further metal plating pattern layer “B′” is different from that of the metal plating pattern layer “B”.

6. The electronic component package according to claim 1 , wherein at least a part of the metal plating pattern layers “A” and/or “B” serves as a heat-releasing part of the electronic component package.

7. The electronic component package according to claim 1 , wherein the dry plating layer has a thickness of 100 nm to 1000 nm, whereas the wet plating layer has a thickness of 4 μm to 500 μm.

8. The electronic component package according to claim 1 , wherein the dry plating layer comprises at least one kind of a metal material selected from a group consisting of Ti, Cr and Ni, whereas the wet plating layer comprises at least one kind of a metal material selected from a group consisting of Cu, Ni and Al.

9. The electronic component package according to claim 1 , wherein a light-emitting element is provided as the electronic component, and
instead of the sealing resin layer, a fluorescent layer is provided surrounding the light-emitting element, and also a transparent resin layer is provided such that the light-emitting element and the fluorescent layer are covered with the transparent resin layer.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Sawada Susumu
• Nakatani Seiichi
• Yamashita Yoshihisa
• Kawakita Koji

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title