Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same

Patent metadata

Field	Value
Publication number	US-9449888-B2
Application number	US-201514594259-A
Country	US
Kind code	B2
Filing date	Jan 12, 2015
Priority date	Mar 28, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

First claim

What is claimed is:

1. A method for forming an integrated circuit structure, the method comprising:
forming a deep n-well (DNW) in a substrate;
forming a PMOS transistor in the DNW;
forming an NMOS transistor in the substrate and outside the DNW;
forming a dissipation device, wherein the dissipation device comprises a reverse-biased diode in the substrate between the PMOS transistor and the NMOS transistor;
forming a substrate pickup, wherein the dissipation device is connected to the substrate pickup; and
forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor, wherein the dissipation device is also connected to the electrical path.

2. The method of claim 1 , wherein the dissipation device comprises an n-type diode.

3. The method of claim 1 , wherein a breakdown voltage of the dissipation device is lower than a breakdown voltage or a gate tunneling voltage of the NMOS transistor.

4. The method of claim 1 , wherein the DNW has accumulated positive charges from plasma processing.

5. The method of claim 1 , wherein the dissipation device is connected to the gate structure of the NMOS transistor at a same metal level or at a lower metal level than the connection between the drain of the PMOS transistor and the gate structure of the NMOS transistor on the electrical path.

6. The method of claim 1 , wherein forming the dissipation device comprises forming the dissipation device outside the DNW.

7. A method of forming an integrated circuit (IC) structure, the method comprising:
forming a deep n-well (DNW) in a substrate;
forming a p-channel metal-oxide-semiconductor (PMOS) transistor inside the DNW;
forming a first n-channel metal-oxide-semiconductor (NMOS) transistor formed in the substrate and outside the DNW;
forming a dissipation device in the substrate, wherein the dissipation device is connected to a substrate pickup; and
forming an electrical path between a gate structure of the PMOS transistor and a drain of the first NMOS transistor, wherein the dissipation device is connected to the electrical path.

8. The method of claim 7 , forming a second NMOS transistor inside the DNW.

9. The method of claim 7 , wherein forming the dissipation device comprises forming the dissipation device in a p-well, wherein the first NMOS transistor is in the p-well.

10. The method of claim 7 , wherein forming the dissipation device comprises forming the dissipation device separate from the DNW and separate from a well associated with the first NMOS transistor.

11. The method of claim 7 , wherein forming the dissipation device comprises forming an n-doped region in the substrate.

12. The method of claim 7 , further comprising forming the substrate pickup on an opposite side of the first NMOS transistor from the PMOS transistor.

13. The method of claim 7 , wherein forming the electrical path between the gate structure of the PMOS transistor and the drain of the first NMOS transistor comprises forming the electrical path on a plurality of metal levels of the IC structure.

14. The method of claim 7 , wherein forming the DNW comprises accumulating ions from at least one plasma process in the DNW.

15. A method of forming an integrated circuit (IC) structure, the method comprising:
forming a deep n-well (DNW) in a substrate;
forming a first metal-oxide-semiconductor (MOS) transistor of a first conductivity type in the substrate;
forming a second MOS transistor in the substrate, wherein the second MOS transistor is in an n-well in the substrate;
forming a dissipation device in the n-well;
forming a third MOS transistor in the substrate, wherein the third MOS transistor has a second conductivity type, and the second conductivity type is opposite to the first conductivity type; and
forming an electrical path between a drain of the second MOS transistor and a gate structure of the first MOS transistor, wherein the dissipation device is connected to the electrical path.

16. The method of claim 15 , further comprising forming a substrate pickup in the n-well, wherein the dissipation device is electrically connected to the substrate pickup.

17. The method of claim 16 , wherein forming the substrate pickup comprises forming the substrate pickup on an opposite side of the dissipation device from the second MOS transistor.

18. The method of claim 15 , wherein forming the electrical path between the drain of the second MOS transistor and the gate structure of the first MOS transistor comprises forming the electrical path on a plurality of metal levels of the IC structure.

19. The method of claim 15 , wherein forming the first MOS transistor comprises forming the first MOS transistor in the DNW.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yen David
• Lin Sung-Chieh
• Hsu Kuoyuan (Peter)

Classifications

• H10P34/40

  with high-energy radiation · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title