Self-forming barrier for subtractive copper

Patent metadata

Field	Value
Publication number	US-9449874-B1
Application number	US-201514755780-A
Country	US
Kind code	B1
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.

First claim

What is claimed is:

1. A method of forming electrically conductive structures comprising:
forming at least one copper containing layer including a barrier forming element;
applying a first anneal to the at least one copper containing layer, wherein the first anneal increases grain size of copper in said at least one copper containing layer;
etching the at least one copper containing layer to provide a plurality of copper containing lines;
depositing a dielectric fill in a space between adjacent copper containing lines; and
applying a second anneal to the plurality of copper containing lines, wherein during said second anneal said barrier forming element diffuse to an interface between sidewalls of the plurality of the copper containing pillars and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.

2. The method of claim 1 , wherein the barrier forming element comprises manganese (Mn).

3. The method of claim 1 , wherein the forming of the copper containing layer including the barrier forming element comprises:
forming a first layer of barrier material on a substrate;
forming a seed layer containing the barrier forming element on the first layer of the barrier material; and
forming a copper layer on the seed layer, wherein the seed layer and the copper layer provide the at least one copper containing layer including the barrier forming element.

4. The method of claim 3 further comprising forming a second layer of barrier material on the copper layer.

5. The method of claim 4 , wherein said applying the first anneal to the at least one copper containing layer diffuses said barrier forming element from the seed layer to the first and second layer of barrier material.

6. The method of claim 1 , wherein the first anneal increases grain size of said copper in said at least one copper containing layer from a fine grain size that ranges from 50 nm to 1250 nm to a larger grain size that ranges from 350 nm to 3000 nm.

7. The method of claim 1 , wherein said applying said first anneal comprises a temperature ranging from 50° C. to 500° C., and the second anneal comprises a temperature ranging from 50° C. to 500° C.

8. The method of claim 1 , wherein depositing the dielectric fill comprises a silicon and oxygen containing dielectric.

9. The method of claim 1 , wherein the barrier layer comprises an oxide including elements from the dielectric fill and the barrier forming element.

10. A method of forming electrically conductive structures comprising:
forming at least one copper containing layer on a manganese containing seed layer;
applying a first anneal to the at least one copper containing layer, wherein the first anneal increases grain size of said copper in said at least one copper containing layer;
etching the at least one copper containing layer to provide a plurality of copper containing lines;
depositing a dielectric fill in a space between adjacent copper containing lines; and
applying a second anneal to the plurality of copper containing lines to diffuse manganese from the manganese containing seed layer to an interface between sidewalls of the plurality of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.

11. The method of claim 10 , wherein the manganese containing seed layer is an alloy of manganese and copper.

12. The method of claim 10 , wherein the forming of the at least one copper containing layer comprises:
forming a first layer of barrier material on a substrate;
forming the manganese containing seed layer on the first layer of the barrier material; and
plating the at least one copper layer on the seed layer, wherein the seed layer and the copper layer provide the at least one copper containing layer including the barrier forming element.

13. The method of claim 12 further comprising forming a second layer of barrier material on the at least one copper containing layer.

14. The method of claim 13 , wherein said applying the first anneal to the at least one copper containing layer diffuses manganese from the manganese containing seed layer to the first and second layer of barrier material.

15. The method of claim 13 , wherein the first anneal increases grain size of copper in said at least one copper containing layer from a fine grain size ranging from 50 nm to 1250 nm to a large grain size ranging from 350 nm to 3000 nm.

Assignees

• IBM

Inventors

• Standaert Theodorus E
• Paruchuri Vamsi K

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title