Embedded package substrate capacitor with configurable/controllable equivalent series resistance

US9449762B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9449762-B2
Application numberUS-201414272356-A
CountryUS
Kind codeB2
Filing dateMay 7, 2014
Priority dateMay 7, 2014
Publication dateSep 20, 2016
Grant dateSep 20, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

First claim

Opening claim text (preview).

What is claimed is: 1. A capacitor structure, comprising: a first electrode comprising a first surface and an opposing second surface; a second electrode comprising a third surface and an opposing fourth surface; a first dielectric layer coupled to and separating the first and second electrodes; and a first equivalent series resistance (ESR) control structure, comprising a first ESR value, coupled to the first electrode, the first ESR control structure comprising: a second dielectric layer coupled to the first surface of the first electrode; a first metal layer coupled to a first surface of the second dielectric layer; and a first set of pillars embedded in the second dielectric layer and extending between the first electrode and the first metal layer; further comprising a second ESR control structure, comprising a second ESR value different from the first ESR value, coupled to the first electrode, the second ESR control structure comprising: a third dielectric layer coupled to the second surface of the first electrode; a second metal layer coupled to a first surface of the third dielectric layer; and a second set of pillars embedded in the third dielectric layer and extending between the first electrode and the second metal layer. 2. The capacitor structure of claim 1 , wherein the first surface of the first electrode is an upper surface and the second surface of the first electrode is a lower surface. 3. The capacitor structure of claim 1 , wherein a total number of pillars in the first set of pillars is the same as a total number of pillars in the second set of pillars. 4. The capacitor structure of claim 1 , wherein a total number of pillars in the first set of pillars is different than a total number of pillars in the second set of pillars. 5. A capacitor structure, comprising: a first electrode comprising a first surface and an opposing second surface; a second electrode comprising a third surface and an opposing fourth surface; a first dielectric layer coupled to and separating the first and second electrodes; and a first equivalent series resistance (ESR) control structure coupled to the first electrode, the first ESR control structure comprising: a second dielectric layer coupled to the first surface of the first electrode; a first metal layer coupled to a first surface of the second dielectric layer; and a first set of pillars embedded in the second dielectric layer and extending between the first electrode and the first metal layer, further comprising a second ESR control structure coupled to the second electrode, the second ESR control structure comprising: a third dielectric layer coupled to the third surface of the second electrode; a second metal layer coupled to a first surface of the third dielectric layer; and a second set of pillars embedded in the third dielectric layer and extending between the second electrode and the second metal layer. 6. A capacitor structure, comprising: a first electrode comprising a first surface and an opposing second surface; a second electrode comprising a third surface and an opposing fourth surface; a first dielectric layer coupled to and separating the first and second electrodes; and a first equivalent series resistance (ESR) control structure coupled to the first electrode, the first ESR control structure comprising: a second dielectric layer coupled to the first surface of the first electrode; a first metal layer coupled to a first surface of the second dielectric layer; and a first set of pillars embedded in the second dielectric layer and extending between the first electrode and the first metal layer; a second ESR control structure coupled to the first electrode, the second ESR control structure comprising: a third dielectric layer coupled to the second surface of the first electrode; a second metal layer coupled to a first surface of the third dielectric layer; and a second set of pillars embedded in the third dielectric layer and extending between the first electrode and the second metal layer. 7. The capacitor structure of claim 6 , wherein a total number of pillars in the first set of pillars is the same as a total number of pillars in the second set of pillars. 8. The capacitor structure of claim 6 , wherein a total number of pillars in the first set of pillars is the different than a total number of pillars in the second set of pillars. 9. The capacitor structure of claim 8 , wherein a number of pillars in the first set of pillars is selected based on a desired (ESR) value.

Assignees

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Classifications

  • Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • Piezoelectric device making · CPC title

  • Non-printed capacitor · CPC title

  • associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

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What does patent US9449762B2 cover?
Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the …
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).