Signal handling apparatus for radio frequency circuits

Patent metadata

Field	Value
Publication number	US-9449749-B2
Application number	US-201314025069-A
Country	US
Kind code	B2
Filing date	Sep 12, 2013
Priority date	May 28, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A signal handler providing high linearity in a small size, applicable across wide operating frequencies and bandwidths, while also adapted to preferred integrated circuit (IC) and printed circuit board technologies. In one implementation, a signal handling apparatus includes an input impedance transformer for receiving an input signal and matching an internal apparatus impedance, a splitter for providing N split signals, a number of signal processing circuits for processing the N split signals, a combiner for combining the N split signals into a combined signal, and output impedance transformer for receiving the combined signal and for matching the internal apparatus impedance to an output impedance of the apparatus. The apparatus may provide filtering, duplexing and other radio frequency signal processing functions. A tunable duplexer may be implemented using a vector inductor and tunable capacitor array with frequency dependent impedance transformers.

First claim

What is claimed is:

1. An apparatus comprising:
a first impedance transformer, for receiving an input signal, and matching an input impedance of the apparatus to an internal apparatus impedance;
a splitter, for splitting an output of the first impedance transformer into N split signals;
a plurality of signal processing circuits, for processing the N split signals, wherein at least one of the plurality of signal processing circuits includes a duplexer, the duplexer includes a high band filter circuit and a low band filter circuit, wherein at least one of the high band filter circuit and the low band filter circuit includes a resonator, the resonator including at least one vector inductor;
a combiner, for combining the N split signals into a combined signal; and
a second impedance transformer, for receiving the combined signal, and for matching the internal apparatus impedance to an output impedance of the apparatus.

2. The apparatus of claim 1 wherein the splitter, signal processing circuits, and combiner have respective input and output impedances equivalent to the internal apparatus impedance.

3. The apparatus of claim 1 wherein a selected one of the plurality of signal processing circuits is coupled to filter a corresponding one of the N split signals.

4. The apparatus of claim 1 wherein at least one of the plurality of signal processing circuits is a filter circuit.

5. The apparatus of claim 1 wherein the at least one vector inductor comprises a plurality, M, of mutual, tightly coupled, layered, inductive structures.

6. The apparatus of claim 5 wherein the vector inductor further comprises:
a plurality, M, of inductor elements disposed as a corresponding plurality of circuit layers, the inductor elements each formed as a patch of conductive material, and the circuit layers arranged vertically with respect to one another such that the patches of conductive material of the inductor elements are vertically aligned with one another;
a plurality of insulating material layers disposed between respective pairs of the circuit layers carrying the inductor elements; and
wherein each respective inductor element is tightly coupled to one or more adjacent inductor elements disposed in a circuit layer above and/or below the respective inductor element.

7. The apparatus of claim 6 wherein each inductor element is formed as a generally rectangular patch of conductive material.

8. The apparatus of claim 6 wherein the circuit layers and insulating material layers for each inductor are formed on a microstrip circuit board.

9. The apparatus of claim 6 wherein at least one of the resonators further comprises:
an array capacitor providing an adjustable capacitance, the array capacitor formed from a plurality of capacitance cells, each capacitance cell further coupled between the first and second terminals, each unit capacitance cell comprising a pair of passive, two-terminal capacitor components, each capacitor component having an anode terminal and a cathode terminal and a bias voltage input terminal, the pair of capacitors connected in anti-parallel, such that an anode of a first capacitor is connected to a cathode of a second capacitor, and an anode of the second capacitor is connected to a cathode of the first capacitor.

10. The apparatus of claim 9 wherein the array capacitor is formed on a semiconductor chip substrate.

11. The apparatus of claim 10 wherein the array capacitor semiconductor chip is mounted to the printed circuit board that provides the vector inductor structure.

12. The apparatus of claim 1 wherein at least one of the resonators further comprise an array of capacitors.

13. The apparatus of claim 12 wherein the at least one resonator is tunable by changing a capacitance of the capacitor array.

14. The apparatus of claim 13 wherein the resonators further comprise frequency dependent matching networks to enable a constant frequency response under frequency scaling.

15. The apparatus of claim 14 wherein the frequency dependent matching networks adjust to a change in the internal impedance of the apparatus as a result of a change in the capacitance of the capacitor array.

16. An apparatus comprising:
a first impedance transformer, for receiving an input signal, and matching an input impedance of the apparatus to an internal apparatus impedance;
a splitter, for splitting an output of the first impedance transformer into N split signals;
a plurality of signal processing circuits, for processing the N split signals;
a combiner, for combining the N split signals into a combined signal; and
a second impedance transformer, for receiving the combined signal, and for matching the internal apparatus impedance to an output impedance of the apparatus,
wherein the input impedance is K ohms, the internal impedance is R ohms, and the first impedance transformer further reduces a voltage of the input signal by a factor of

K
R

.

17. The apparatus of claim 16 wherein at least one of the signal processing circuits includes a duplexer that further includes high band and low band filter circuits.

18. The apparatus of claim 16 wherein the splitter further drops a voltage level by a factor of √{square root over (N)}.

19. A method for handling an input signal comprising:
a first step of impedance transforming to transform an input impedance to match an internal impedance;
splitting an output of the first step of impedance transforming into N split signals;
signal processing the N split signals, wherein the signal processing performs a duplexing function and filtering of a corresponding one of the N split signals, the filtering performed using resonators including at least one vector inductor;
combining the N split signals into a combined signal; and
a second step of impedance transforming, for matching an internal impedance to an output impedance, and to provide an output signal.

20. The method of claim 19 wherein the splitting, signal processing, and combining steps provide respective input and output impedances equivalent to the internal impedance.

21. The method of claim 19 wherein the at least one vector inductor comprises a plurality, M, of mutual, tightly coupled, layered, inductive structures.

22. The method of claim 19 wherein at least one of the resonators further comprise an array of capacitors.

23. A method for handling an input signal comprising:
a first step of impedance transforming to transform an input impedance to match an internal impedance;
splitting an output of the first step of impedance transforming into N split signals;
signal processing the N split signals;
combining the N split signals into a combined signal; and
a second step of impedance transforming, for matching an internal impedance to an output impedance, and to provide an output signal, wherein the input impedance is K ohms, the internal impedance is R ohms, and the first step of impedance transforming further reduces a voltage of the input signal by a factor of

K
R

.

24. The method of claim 23 wherein the signal pr

Assignees

• Tdk Corp

Inventors

• Gupta Dev V
• Lai Zhiguo
• Moussa Medhi Si

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/931

  Shapes of bond pads · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title