Method for setting a flash memory for HTOL testing

Patent metadata

Field	Value
Publication number	US-9449718-B2
Application number	US-201414566060-A
Country	US
Kind code	B2
Filing date	Dec 10, 2014
Priority date	May 9, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage.

First claim

What is claimed is:

1. A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing, the flash memory comprising a substrate including a source region and a drain region, and a control gate, the method comprising:
setting the voltages that are applied to the source region, the control gate, and the substrate when the flash memory is in a standby mode, where setting the voltages further comprises:
setting a first voltage that is applied to the source region to a ground voltage,
setting a second voltage that is applied to the control gate to the ground voltage, and
setting a third voltage that is applied to the substrate to a power supply voltage that is higher than the ground voltage,

wherein a charge leakage between the control gate and the substrate is reduced and a charge storage capability of the control gate is improved by applying the ground voltage to both the control gate and the source region when the flash memory is in the standby mode.

2. The method according to claim 1 , wherein the flash memory further includes a select gate, the method further comprising:
setting a fourth voltage that is applied to the select gate to the power supply voltage.

3. The method according to claim 1 , further comprising:
setting a fifth voltage that is applied to the drain region to an operating voltage.

4. The method according to claim 2 , wherein the power supply voltage is set to 1.8V.

5. The method according to claim 3 , wherein the operating voltage is set to 1.8V.

6. The method according to claim 1 , wherein the ground voltage is set to 0V.

7. The method according to claim 1 , wherein the flash memory includes a p-type metal-oxide-semiconductor (PMOS) transistor.

8. The method according to claim 3 , wherein the substrate is doped with an n-type dopant, and the source region and the drain region are doped with a p-type dopant.

9. The method according to claim 1 , wherein the flash memory is a NOR flash memory.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp

Inventors

• Chan Yipeng
• Kim Kijun
• Zhao Guoxu
• Ye Xiao
• Yang Zhen

Classifications

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/06

  Acceleration testing · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C16/30

  Power supply circuits · CPC title