Adaptive dual voltage write driver with dummy resistive path tracking
US-2015043271-A1 · Feb 12, 2015 · US
Resistive memory device, resistive memory system and method of operating the resistive memory device
US9449686B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9449686-B2 |
| Application number | US-201514743488-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 18, 2015 |
| Priority date | Oct 28, 2014 |
| Publication date | Sep 20, 2016 |
| Grant date | Sep 20, 2016 |
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Abstract
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A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
First claim
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What is claimed is: 1. A method of operating a resistive memory device, wherein the resistive memory device comprises a plurality of bit lines and at least one dummy bit line, the method comprising: detecting a first address accompanying a first command related to a memory operation of the resistive memory device; generating a plurality of inhibit voltages for biasing non-selected lines from among the plurality of bit lines; and providing to a first dummy bit line from among t…
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Physics · mapped topic
- G11C13/004Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9449686B2 cover?
- A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-select…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C13/004. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).