Conflict detection for self-aligned multiple patterning compliance

Patent metadata

Field	Value
Publication number	US-9449140-B2
Application number	US-201514967481-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Jan 23, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

First claim

What is claimed is:

1. A system for performing design layout, comprising:
a graph component configured to:
receive an initial design layout associated with an electrical component; and
generate a conflict graph from the initial design layout, the conflict graph comprising one or more nodes coupled by one or more edges, an edge, between a first node and a second node, comprising an edge type identified based upon a space, between a first polygon represented by the first node and a second polygon represented by the second node, corresponding to a spacing threshold range assigned to the edge type; and

a conflict detection component configured to:
for respective loops within the conflict graph, identify a conflict associated with the initial design layout based upon a loop comprising an odd number of nodes.

2. The system of claim 1 , the graph component configured to:
responsive to the conflict graph comprising at least one same-process edge, cluster a first cluster one node and a second cluster one node coupled by a first same-process edge into a first multi-node cluster for inclusion within the conflict graph; and
for respective unclustered nodes, include an unclustered node as a single node cluster within the conflict graph.

3. The system of claim 1 , comprising:
a conflict resolution component configured to:
responsive to a modification of the initial design layout to resolve the conflict, generate a design layout based upon the modification of the initial design layout;
generate one or more mandrel pattern layers for the design layout, a mandrel pattern layer comprising mandrel surrounded at least in part by spacer; and
generate one or more trim pattern layers for the design layout.

4. The system of claim 1 , the edge type comprising at least one of a same-process edge type or a different-process edge type.

5. A method for performing design layout, comprising:
receiving an initial design layout associated with an electrical component;
generating a conflict graph from the initial design layout, the conflict graph comprising:
a first node representing a first polygon of the initial design layout;
a second node representing a second polygon of the initial design layout, the second node coupled to the first node by a same-process edge; and
a third node representing a third polygon of the initial design layout, the third node coupled to the second node by a different-process edge;

updating the conflict graph to remove the same-process edge and generate an updated conflict graph; and
for respective loops within the updated conflict graph, identifying a conflict associated with the initial design layout based upon a loop comprising an odd number of nodes, wherein the method is implemented by a processing unit that executes processor-executable instructions stored on a non-transitory computer-readable medium.

6. The method of claim 5 , comprising:
selecting the same-process edge for coupling the first node to the second node based upon a spacing between the first node and the second node corresponding to a first spacing threshold range; and
selecting the different-process edge for coupling the second node to the third node based upon a spacing between the second node and the third node corresponding to a second spacing threshold range.

7. The method of claim 5 , the updating comprising:
clustering the first node and the second node into a multi-node cluster responsive to the second node being coupled to the first node by the same-process edge.

8. The method of claim 7 , the loop comprising the multi-node cluster, the third node, and the different-process edge.

9. The method of claim 7 , the third node coupled to the first node by a second different-process edge.

10. The method of claim 9 , the loop comprising the multi-node cluster, the third node, the different-process edge, and the second different-process edge.

11. The method of claim 5 , comprising displaying the conflict within a visualization of the initial design layout.

12. The method of claim 11 , the displaying comprising:
providing a spacing constraint recommendation for the conflict.

13. The method of claim 5 , comprising:
modifying the initial design layout to resolve the conflict and to generate a modified initial design layout.

14. The method of claim 13 , the modifying the initial design layout comprising:
applying at least one of a min space rule, an island rule, an isolated trench rule, a corner-to-corner rule, or a flip assignment rule to the initial design layout.

15. A method for performing design layout, comprising:
receiving an initial design layout associated with an electrical component;
generating a conflict graph from the initial design layout, the conflict graph comprising:
a first node representing a first polygon of the initial design layout;
a second node representing a second polygon of the initial design layout, the second node coupled to the first node by a same-process edge; and
a third node representing a third polygon of the initial design layout, the third node coupled to the second node by a different-process edge;

clustering the first node and the second node into a multi-node cluster responsive to the second node being coupled to the first node by the same-process edge to generate an updated conflict graph; and
for respective loops within the updated conflict graph, identifying a conflict associated with the initial design layout based upon a loop comprising an odd number of nodes, wherein the method is implemented by a processing unit that executes processor-executable instructions stored on a non-transitory computer-readable medium.

16. The method of claim 15 , comprising displaying the conflict within a visualization of the initial design layout.

17. The method of claim 16 , the displaying comprising:
providing a spacing constraint recommendation for the conflict.

18. The method of claim 15 , comprising:
modifying the initial design layout to resolve the conflict and to generate a modified initial design layout.

19. The method of claim 18 , the modifying the initial design layout comprising:
applying at least one of a min space rule, an island rule, an isolated trench rule, a corner-to-corner rule, or a flip assignment rule to the initial design layout.

20. The method of claim 15 , the loop comprising the multi-node cluster, the third node, and the different-process edge.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chin-Chang
• Lin Hunglung
• Shen Ying-Yu
• YANG Wen-ju
• Hsieh Ken-Hsien

Classifications

• G03F7/70475

  Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F7/70466

  Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5072

  Physics · mapped topic