System and method for tracing a net

Patent metadata

Field	Value
Publication number	US-9449139-B2
Application number	US-201514609996-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jul 3, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net.

First claim

What is claimed is:

1. A method of tracing a net, comprising:
comparing an IC design against a marked portion of the IC design;
extracting a traced net that includes the marked portion from the IC design, wherein extracting the traced net comprises:
identifying a net identification (NETID) of the marked portion, and
overwriting a NETID of conductive portions of the traced net to match the NETID of the marked portion;

displaying the traced net on a user interface, wherein displaying the traced net comprises displaying an identified variance, if any, between the IC design and the traced net; and
storing at least one indicator along with information identifying the traced net.

2. The method of claim 1 wherein the marked portion of the IC design designated by a user is designated by a graphic shape being drawn around a conductive pattern designated as the marked portion.

3. The method of claim 1 wherein the marked portion of the IC design designated by a user is designated by a text label placed over a conductive pattern designated as the marked portion.

4. The method of claim 1 wherein the marked portion of the IC design designated by a user is designated by at least one graphic point having an X axis component and a Y axis component identifying an area containing a conductive pattern designated as the marked portion.

5. The method of claim 1 wherein the marked portion of the IC design designated by a user is designated by at least two graphic points each having an X axis component and a Y axis component identifying a corner of an area containing a conductive pattern designated as the marked portion.

6. The method of claim 1 wherein the IC design file is a mini-tech file.

7. The method of claim 1 wherein displaying the traced net includes an additional visual indication identifying the traced net including at least one of changed color, shading, patterning or size of the traced net.

8. The method of claim 1 wherein the at least one indicator indicates the traced net is erroneous.

9. A method of tracing a net, comprising:
comparing an IC design against a marked portion of the IC design, the marked portion of the IC design having a net identification (NETID);
identifying one or more conductive portions of the IC design electrically connected to the marked portion, each conductive portion of the conductive portions that are not in a same net with marked portion having a NETID different than the NETID of the marked portion;
overwriting the NETID of the conductive portions with the NETID of the marked portion, the conductive portions and marked portion forming the traced net;
displaying the traced net on a user interface, wherein displaying the traced net comprises displaying an identified variance, if any, between the IC design and the traced net; and
storing at least one indicator with information identifying the traced net.

10. The method of claim 9 wherein, prior to overwriting, the NETID of the marked portion and each NETID of the conductive portions are unique in the IC design.

11. The method of claim 9 wherein one or more of the conductive portions are on multiple levels.

12. The method of claim 11 wherein the conductive portions on multiple levels are electrically connected through at least one via.

13. The method of claim 9 wherein the conductive portions are identified prior to overwriting each of the NETIDs of the conductive portions.

14. The method of claim 9 wherein each of the conductive portions are identified and the corresponding NETID of the identified conductive portions is overwritten with the NETID of the marked portion.

15. A system, comprising:
a computer-readable storage medium containing data representing an integrated circuit (IC) design, the IC design comprising a plurality of portions, and instructions for causing, if executed by a processor, the processor to perform a net tracer method; and
a processor coupled to read the storage medium, the processor configured for:
comparing an IC design against a marked portion of the IC design the marked portion of the IC design having a net identification (NETID);
identifying conductive portions of the IC design electrically connected to the marked portion, the conductive portions each having a net identification (NETID) different than the NETID of the marked portion;
overwriting the NETID of the conductive portions with the NETID of the marked portion, the conductive portions and marked portion forming the traced net;
displaying the traced net on a user interface with an additional visual indication identifying the traced net including at least one of changed color, shading, patterning or size of the traced net, wherein displaying the traced net comprises displaying an identified variance, if any, between the IC design and the traced net.

16. The system of claim 15 wherein, prior to overwriting, the NETID of the marked portion and each NETID of the conductive portions are unique in the IC design.

17. The system of claim 15 wherein at least one of the conductive portions is on multiple levels.

18. The system of claim 17 wherein the conductive portions on multiple levels are electrically connected through at least one via.

19. The system of claim 15 wherein the conductive portions are identified prior to overwriting each of the NETIDs of the conductive portions.

20. The system of claim 15 wherein each of the conductive portions are identified and the corresponding NETID of the identified conductive portions are overwritten with the NETID of the marked portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Feng Ming
• Huang Li
• Chen zhen-yi
• Zhang ya-min
• Huang Mu-Jen

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5077

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic