Extracting system architecture in high level synthesis

Patent metadata

Field	Value
Publication number	US-9449131-B2
Application number	US-201414294062-A
Country	US
Kind code	B2
Filing date	Jun 2, 2014
Priority date	Jun 2, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.

First claim

What is claimed is:

1. A method, comprising:
determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description;
determining that the second function is a data consuming function of the first function;
automatically generating, within a circuit design and using a processor, a port comprising a local memory, wherein the port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design; and
automatically generating, within the circuit design, control circuitry controlling operation of the second circuit block by performing handshake signaling between the first circuit block and the second circuit block as a non-self-synchronized port.

2. The method of claim 1 , wherein automatically generating control circuitry comprises:
generating a start control circuit and an end control circuit implementing the flow control construct.

3. The method of claim 1 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block or a third circuit block according to a condition of the control flow construct; and
generating an end control circuit that provides a start control signal to a fourth circuit block responsive receiving a done control signal from either the second circuit block or the third circuit block;
wherein the fourth circuit block is generated from a function that is a data consuming function of the second function or the third function.

4. The method of claim 1 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block according to a condition of the control flow construct; and
generating an end control circuit that provides a start control signal to a third circuit block responsive to receiving a done control signal from the second circuit block;
wherein the third circuit block is generated from a third function that is a data consuming function of the second function.

5. The method of claim 1 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block; and
generating an end control circuit that provides a start control signal to a third circuit block responsive to determining that an end condition of the control flow construct is met;
wherein the third circuit block is generated from a third function that is a data consuming function of the second function.

6. The method of claim 5 , wherein the start control circuit communicates the end condition of the flow control construct to the end control circuit.

7. The method of claim 6 , wherein the end control circuit provides the start control signal to the third circuit block responsive to both the start control circuit and the end control circuit detecting the end condition.

8. A system, comprising:
a processor programmed to initiate executable operations comprising:
determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description;
determining that the second function is a data consuming function of the first function;
automatically generating, within a circuit design, a port comprising a local memory;
wherein the port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design; and
wherein the processor further initiates executable operations comprising:
automatically generating, within the circuit design, control circuitry controlling operation of the second circuit block by performing handshake signaling between the first circuit block and the second circuit block as a non-self-synchronized port.

9. The system of claim 8 , wherein automatically generating control circuitry comprises:
generating a start control circuit and an end control circuit implementing the flow control construct.

10. The system of claim 8 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block or a third circuit block according to a condition of the control flow construct; and
generating an end control circuit that provides a start control signal to a fourth circuit block responsive receiving a done control signal from either the second circuit block or the third circuit block;
wherein the fourth circuit block is generated from a function that is a data consuming function of the second function or the third function.

11. The system of claim 8 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block according to a condition of the control flow construct; and
generating an end control circuit that provides a start control signal to a third circuit block responsive to receiving a done control signal from the second circuit block;
wherein the third circuit block is generated from a third function that is a data consuming function of the second function.

12. The system of claim 8 , wherein automatically generating control circuitry comprises:
generating a start control circuit that, responsive to receiving a done control signal from the first circuit block, outputs a start control signal to the second circuit block; and
generating an end control circuit that provides a start control signal to a third circuit block responsive to determining that an end condition of the control flow construct is met;
wherein the third circuit block is generated from a third function that is a data consuming function of the second function.

13. The system of claim 12 , wherein the start control circuit communicates the end condition of the flow control construct to the end control circuit.

14. The system of claim 13 , wherein the end control circuit provides the start control signal to the third circuit block responsive to both the start control circuit and the end control circuit detecting the end condition.

15. A non-transitory computer-readable storage medium having instructions stored thereon which, when executed by a processor, perform a method comprising:
determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description;
determining that the second function is a data consuming function of the first function;
automatically generating, within a circuit design, a port comprising a local memory;
wherein the port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design; and
automatically generating, within the circuit design, control circuitry controlling operation of the second circuit block by performing handshake signaling between the first circuit

Assignees

• Xilinx Inc

Inventors

• Han Guoling
• Neuendorffer Stephen A

Classifications

• G06F2117/08

  HW-SW co-design, e.g. HW-SW partitioning · CPC title

• G06F8/433 Primary

  Dependency analysis; Data or control flow analysis · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/30

  Circuit design · CPC title