Memory heaps in a memory model for a unified computing system

Patent metadata

Field	Value
Publication number	US-9448930-B2
Application number	US-201514833850-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Mar 29, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

First claim

What is claimed is:

1. A method of allocating memory in a processing system, the method comprising:
receiving a memory instruction from the processing system, wherein the memory instruction references a memory address shared by at least two processors, and
mapping the memory instruction to one of a plurality of virtual memory pools based on the memory address; and
providing a mapping result to the processing system.

2. The method of claim 1 , wherein at least one virtual memory pool is associated with at least one physical memory resource.

3. The method of claim 2 , wherein the at least one physical memory resource is at least two physical memory resources.

4. The method of claim 1 , wherein at least one of the virtual memory pools is not accessible by one of the at least two processors, and at least one of the virtual memory pools is accessible by all of the at least two processors.

5. The method of claim 4 , wherein at least one virtual memory pool is only accessible by a single group of first processor threads.

6. The method of claim 5 , wherein at least one virtual memory pool is only accessible by a single application.

7. The method of claim 1 , wherein at least one virtual memory pool is only accessible by a specific one of the at least two processors.

8. The method of claim 7 , wherein at least one virtual memory pool is mapped to the physical memory upon initiation of an associated processor thread.

9. The method of claim 1 , wherein at least one virtual memory pool is accessible by all of the at least two processors and the at least one virtual memory pool is mapped to a physical memory resource associated with one processor of the at least two processors using a page table associated with the one processor.

10. The method of claim 1 , wherein at least one virtual memory pool is only accessible by a specific type of processor.

11. The method of claim 1 , wherein a type of processor imparts different attributes on a mapped memory.

12. A system having at least two processors, comprising:
a plurality of virtual memory pools, each being configured to access an associated memory resource;
a mapper configured to receive a memory instruction from the system, the memory instruction including a shared memory address (SMA) reference; and
the mapper further configured to map the memory instruction to one of the plurality of virtual memory pools based on the SMA.

13. The system of claim 12 , wherein different attributes are applied to a mapped virtual memory pool depending upon origination of the memory instruction.

14. The system of claim 12 , further comprising:
a shared memory address space, wherein the memory instruction references the SMA in the shared memory address space.

15. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is mapped to a first processor memory resource using a page table and is accessible by the at least two processors.

16. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is not accessible by a first processor, at least another virtual memory pool is not accessible by a second processor, and at least another virtual memory pool is accessible by the first processor and the second processor.

17. The system of claim 12 , wherein at least one of the plurality of virtual memory pools is accessible by a first processor, is not accessible by a second processor, and is an allocated memory space in a memory resource associated with the first processor.

18. The system of claim 12 , wherein at least one virtual memory pool is only accessible by a specific one of the at least two processors.

19. The system of claim 12 , wherein at least one virtual memory pool is only accessible by a specific type of processor.

20. The system of claim 12 , wherein a type of processor imparts different attributes on a mapped memory.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Asaro Anthony
• Normoyle Kevin
• Hummel Mark

Classifications

• G06F12/0284 Primary

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F2212/656

  Address space sharing · CPC title