System on chip and verification method thereof

Patent metadata

Field	Value
Publication number	US-9448917-B2
Application number	US-201514680337-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Apr 9, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.

First claim

What is claimed is:

1. A verification method of a system on chip comprising:
receiving, by a processor included in the system on chip, a test generator and an exception handler;
generating, by the processor including the test generator, a test program including an exception-causing instruction based on a test template;
executing, by the processor, a first instruction at a first operating state as the test program is executed;
stopping, by the processor, the execution of the test program when the exception-causing instruction is executed during the execution of the test program;
performing, by the processor, a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program, the fixed instruction sequence including storing context corresponding to the processor; and
resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction having an address next to an address of the exception-causing instruction.

2. The verification method of claim 1 , wherein the resuming the test program comprising:
as a change from the first operating state to the second operating state is made, executing the second instruction (i) on another processor different than the processor executing the first instruction, or (ii) being executed using at least one of a privilege level different from a privilege level of the first instruction and an instruction set different from an instruction set of the first instruction.

3. The verification method of claim 1 , wherein the generating the test program comprises:
reading a first instruction statement included in the test template;
generating the first instruction corresponding to the first instruction statement such that the first instruction is performed at the first operating state;
reading a state modifying instruction statement included in the test template;
generating the exception-causing instruction, the exception-causing instruction including a switch intention about an operating state, the switch intention about the operating state indicating to change a state of operation of the system on chip, the switch intention about the operating state corresponding to the state modifying instruction statement;
reading a second instruction statement next to the state modifying instruction statement; and
generating the second instruction corresponding to the second instruction statement such that the second instruction is performed at the second operating state at a address adjacent to a address of the exception-causing instruction.

4. The verification method of claim 3 , wherein the switch intention about the operating state is detected using a first sub-component of the test generator.

5. A verification method of a system on chip, the system on chip includes a processor and supports at least two instruction sets, the verification method comprising:
receiving, by the processor, a test generator and an exception handler;
generating, by the processor including the test generator, a test program including an exception-causing instruction based on a test template;
executing, by the processor, a first instruction, the first instruction being generated based on a first instruction set of the at least two instruction sets as the test program is executed;
stopping, by the processor, the execution of the test program when the exception-causing instruction is executed during the execution of the test program;
performing, by the processor, a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program, the fixed instruction sequence including storing context corresponding to the processor; and
resuming the test program from a second instruction after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction, and the second instruction being generated depending on a second instruction set of the at least two instruction sets.

6. The verification method of claim 5 , wherein the generating a test program comprises:
reading a first instruction statement included in the test template;
generating the first instruction corresponding to the first instruction statement based on the first instruction set;
reading a state modifying instruction statement included in the test template;
generating the exception-causing instruction, the exception-causing instruction including a switch intention about an instruction set, the switch intention about the instruction set indicating to change a state of the instruction set to be processed, the switch intention about the instruction set corresponding to the state modifying instruction statement;
reading a second instruction statement next to the state modifying instruction statement; and
generating the second instruction corresponding to the second instruction statement based on the second instruction set at a address adjacent to a address of the exception-causing instruction.

7. The verification method of claim 6 , wherein the state modifying instruction statement includes the switch intention about an instruction set.

8. The verification method of claim 7 , wherein the switch intention about an instruction set is detected using a first sub-component of the test generator.

9. The verification method of claim 8 , wherein content of the first instruction and content of the second instruction are detected by a second sub-component of the test generator.

10. The verification method of claim 6 , wherein the switch intention about an instruction set is detected using arguments included in the exception-causing instruction.

11. The verification method of claim 6 , further comprising:
obtaining a modeling result by feeding at least one of the first instruction, the second instruction, and the exception-causing instruction to a reference model, and
the modeling result includes information about a state change of a verification target processor when the at least one of the first instruction, the second instruction, and the exception-causing instruction is executed.

12. The verification method of claim 11 , wherein the obtaining the modeling result comprises:
detecting a switch intention about a processor included in the exception-causing instruction when the verification target processor includes at least two processor cores; and
feeding a no operation instruction to the reference model without feeding the exception-causing instruction when the switch intention about the processor is detected, and
the no operation instruction is used to set a location of a next instruction to be generated without a state change of the reference model.

13. The verification method of claim 11 , wherein
the generated test program is made on a host system on chip that does not include the verification target processor, and
the executing a first instruction, the performing the fixed instruction sequence, and the resuming the test program are done on a system on chip that includes the verification target processor.

14. A verification method of a system on chip, the system on chip including a processor and supports at least two privilege levels, the verification method comprising:
receiving, by the processor, a test generator and an exception handler;
generating, by the processor including the test generator, a test program including an exception-causing instruction based on a test template;
executing, by the processor, a first ins

Assignees

• Park Sung-Boem
• Park Jin-Sung
• Cho Ara
• Samsung Electronics Co Ltd

Inventors

• Park Sung-Boem
• Park Jin-Sung
• Cho Ara

Classifications

• G06F11/3688 Primary

  for test execution, e.g. scheduling of test suites · CPC title

• G06F9/3865 Primary

  using deferred exception handling, e.g. exception flags · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title