Hetergeneous processor apparatus and method

Patent metadata

Field	Value
Publication number	US-9448829-B2
Application number	US-201213730491-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Dec 28, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

First claim

What is claimed is:

1. A processor comprising:
a set of two or more small physical processor cores;
at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; and
virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

2. The processor as in claim 1 wherein the V-P mapping logic is to map each virtual core to a physical core within the set of two or more small physical processor cores to allow a first set of threads to be executed in parallel across the small physical processor cores.

3. The processor as in claim 2 wherein the V-P mapping logic is to map a thread from a virtual core to a large physical processor core transparently to the software in response to detected characteristics associated with the threads being executed.

4. The processor as in claim 3 wherein the detected characteristics associated with the threads being executed comprises the number of threads capable of being executed in parallel drops below a specified threshold.

5. The processor as in claim 1 wherein the small physical processor cores are exposed to the software through a default mapping between virtual cores small physical processor cores.

6. The processor as in claim 5 wherein the large physical processor core is hidden from the software and made accessible to the software only by the V-P mapping logic transparently mapping one or more of the virtual cores to the large physical processor cores.

7. The processor as in claim 1 wherein the V-P mapping logic operates in accordance with a set of mapping rules.

8. The processor as in claim 7 wherein the set of mapping rules is programmable.

9. The processor as in claim 1 further comprising:
logic to monitor current operating conditions associated with the processor;

wherein the V-P mapping logic is to map each virtual core to a large or small physical core based in part on current operating conditions.

10. The processor as in claim 9 wherein the current operating conditions comprise current power usage of the processor in view of a specified power budget, temperature, instructions-per-clock, utilization, or other internal performance metrics wherein the V-P mapping logic is to map each virtual core to a small or large physical core such that the power budget, temperature threshold, instructions-per-clock threshold, or utilization threshold, is maintained.

11. A method implemented in a processor comprising:
providing a set of two or more small physical processor cores;
providing at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; and
exposing the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

12. The method as in claim 11 further comprising:
mapping each virtual core to a physical core within the set of two or more small physical processor cores to allow a first set of threads to be executed in parallel across the small physical processor cores.

13. The method as in claim 12 further comprising:
mapping a thread from a virtual core to a large physical processor core transparently to the software in response to detected characteristics associated with the threads being executed.

14. The method as in claim 13 wherein the detected characteristics associated with the threads being executed comprises the number of threads capable of being executed in parallel drops below a specified threshold.

15. The method as in claim 14 wherein the small physical processor cores are exposed to the software through a default mapping between virtual cores and small physical processor cores.

16. The method as in claim 15 wherein the large physical processor core is hidden from the software and made accessible to the software only by transparently mapping one or more of the virtual cores to the large physical processor cores.

17. The method as in claim 11 wherein mapping is performed in accordance with a set of mapping rules.

18. The method as in claim 17 wherein the set of mapping rules is programmable.

19. The method as in claim 11 further comprising:
monitoring current operating conditions associated with the processor; and
mapping each virtual core to a large or small physical core based in part on the current operating conditions.

20. The method as in claim 19 wherein the current operating conditions comprise current power usage of the processor in view of a specified power budget, temperature, instructions-per-clock, utilization, or other internal performance metrics, wherein each virtual core is mapped to a small or large physical core such that the power budget, temperature threshold, instructions-per-clock threshold, or utilization threshold, is maintained.

Assignees

• Intel Corp

Inventors

• Narvaez Paolo
• Srinivasa Ganapati N
• Gorbatov Eugene
• Subbareddy Dheeraj R
• Naik Mishali
• Naveh Alon
• Prabhakaran Abirami
• Weissmann Eliezer
• Brett Paul
• Hahn Scott D
• Herdrich Andrew J
• Khanna Gaurav
• Fenger Russell J
• Bigbee Bryant E
• Henroid Andrew D
• Koufaty David A

Classifications

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title