Method for the fabrication of thin-film transistors together with other components on a substrate

Patent metadata

Field	Value
Publication number	US-9446946-B2
Application number	US-201514862504-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Oct 20, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method for the fabrication of thin-film transistors together with micromechanical components, other active electrical components or both on an amorphous or polycrystalline substrate includes disposing the thin-film transistors and the other components on different areas of the substrate.

First claim

What is claimed is:

1. A method for the fabrication of thin-film transistors together with micromechanical components, other active electrical components or both on an amorphous or polycrystalline substrate, wherein the thin-film transistors and the other active electrical components are each disposed on different areas of the substrate, the method comprising the stapes of:
applying a first layer of an electrode material to the substrate;
structuring the first layer into drain and source electrodes in an area of the thin-film transistors and into electrodes in an area of other electrical components;
after structuring the first layer, applying a semiconductor layer;
structuring the semiconductor layer such that the drain and source electrodes in the area of the transistors and the electrodes in the area of the other electrical components remain at least partially covered by the semiconductor layer, and that micromechanical components in an area of micromechanical components that are subsequently to have cavities remain covered;
depositing a dielectric layer;
structuring the dielectric layer to a gate dielectric of the thin-film transistors in the area of the transistors, at least partially covering the semiconductor layer above the electrodes in the area of the other electrical components and at least partially removing the semiconductor layer above the micromechanical components in the area of the micromechanical components;
applying a second layer of an electrode material;
structuring the second layer of electrode material into gate electrodes in the area of the transistors, into second electrodes in areas above the semiconductor layer and above the first electrodes ( 102 c ) the area of the other electrical components in and into electrodes that at least partially cover the semiconductor layer in the area of the micromechanical components; and
etching away the semiconductor layer in the area of the micromechanical components.

2. The method according to claim 1 , wherein the other electrical components are fabricated as metal semiconductor diodes.

3. The method according to claim 1 , wherein the step of structuring the first layer includes forming electrodes in the area of the micromechanical components.

4. The method according to one of claim 1 , wherein potassium hydroxide (KOH) is utilized to etch away the semiconductor layer in the area of the micromechanical components.

5. The method according to one of claim 1 , wherein tetramethylammonium hydroxide solution is utilized to etch away the semiconductor layer in the area of the micromechanical components.

6. The method according to claim 1 , wherein the step of structuring the second layer, the electrode material is completely removed in the area of the micromechanical components.

7. The method according to claim 1 , wherein the semiconductor material comprising the semiconductor layer is amorphous or polycrystalline silicon.

8. The method according to claim 1 , wherein the semiconductor material comprising the semiconductor layer is an amorphous or polycrystalline metal oxide, which contains more than 10 percent by weight of indium oxide and/or gallium oxide and/or zinc oxide and/or tin oxide.

9. The method according to claim 1 , further comprising applying an injection layer to the first electrodes before applying the semiconductor layer.

10. The method according to claim 9 , wherein a doped semiconductor layer is applied as the injection layer.

11. The method according to claim 10 , wherein the doped semiconductor layer is selectively deposited on the drain and source electrodes in the area of the thin-film transistors and on the electrodes in an area of other electrical components.

Assignees

• Univ Stuttgart

Inventors

• Schalberger Patrick
• Fruehauf Norbert
• Herrmann Marcus

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title