Wafer-level packaging of integrated devices, and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9446943-B2
Application number	US-201414288130-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 31, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A wafer-level packaging, comprising: a first semiconductor body integrating a MEMS structure; a second semiconductor body, including a surface electrical-contact region and an ASIC coupled to the MEMS structure and to said electrical-contact region; a first coating layer, made of resin, which englobes and protects the first body, the second body, and the electrical-contact region; at least one first conductive through via, which extends through the first coating layer in an area corresponding, and electrically coupled, to the first electrical-contact region; an electrical-contact pad, which extends over the first coating layer, electrically coupled to the first conductive through via; a third semiconductor body, integrating an electronic circuit, glued on the first coating layer; a second coating layer, made of resin, which englobes and protects the third body; at least one second conductive through via, which extends completely through the second coating layer in an area corresponding, and electrically coupled, to the electrical-contact pad; and a further electrical-contact pad electrically coupled to the second conductive through via.

First claim

The invention claimed is:

1. A package comprising:
a first semiconductor body integrating a first microelectromechanical structure;
a second semiconductor body having a first side that includes:
an active region integrating an electronic circuit that is coupled to the first microelectromechanical structure; and
a first electrical-contact region operatively coupled to said electronic circuit;

a first coating layer of resin located over the first semiconductor body and the second semiconductor body and having a first surface;
a first conductive through via extending through the first coating layer and electrically coupled to the first electrical-contact region;
a second electrical-contact region located on the first surface of the first coating layer and electrically coupled to the first conductive through via;
a third semiconductor body integrating a second microelectromechanical structure;
a second coating layer of resin located between the second semiconductor body and the first coating layer and surrounding the third semiconductor body and the first electrical-contact region;
a second conductive through via that extends through the second coating layer and is electrically coupled to the first electrical-contact region; and
a third electrical-contact region located between the first coating layer and the second coating layer and is electrically coupled to the first conductive through via and to the second conductive through via.

2. The package according to claim 1 , wherein the first semiconductor body includes a first electrical-contact pad operatively coupled to the first microelectromechanical structure,
said packaging further comprising:
a third conductive through via that extends through the first coating layer and is electrically coupled to the first electrical-contact pad; and
a fourth electrical-contact region located on the first surface of the first coating layer and is electrically coupled to the third conductive through via.

3. The package according to claim 1 , wherein the first semiconductor body is coupled to the second coating layer by an adhesive layer.

4. The package according to claim 1 , wherein the second semiconductor body includes a fourth electrical-contact region that is on the first side,
said packaging further comprising:
a third conductive through via that extends through the second coating layer and is electrically coupled to the second electrical-contact region; and
a first electrical-contact pad that is located between the first and second coating layers and is electrically coupled to the third conductive through via, wherein the first semiconductor body includes an active surface housing at least a second electrical-contact pad, said second electrical-contact pad of the first semiconductor body being electrically coupled to the first electrical-contact pad by a conductive wire.

5. The package according to claim 1 , wherein the second semiconductor body includes a second electrical-contact region located on the first side, said packaging further comprising:
a third conductive through via that extends through the second coating layer and is electrically coupled to the second electrical-contact region;
a first electrical-contact pad located between the first and second coating layers and is electrically coupled to the third conductive through via; and
a solder ball, wherein the first semiconductor body includes an active surface housing a second electrical-contact pad, said second electrical-contact pad of the first semiconductor body being electrically coupled to the first electrical-contact pad by the solder ball.

6. The package according to claim 1 , wherein said third semiconductor body is surrounded by said second coating layer and in direct contact with said second coating layer.

7. The package according to claim 1 , wherein said first semiconductor body has side surfaces that are covered by said first coating layer and in direct contact with said first coating layer.

8. A package comprising:
a first semiconductor body integrating a first microelectromechanical structure;
a second semiconductor body having a first side that includes:
an active region integrating an electronic circuit that is coupled to the first microelectromechanical structure; and
a first electrical-contact region operatively coupled to said electronic circuit;

a first coating layer of resin located over the first semiconductor body and the second semiconductor body and having a first surface;
a first conductive through via extending through the first coating layer and electrically coupled to the first electrical-contact region;
a second electrical-contact region located on the first surface of the first coating layer and electrically coupled to the first conductive through via;
a solder ball; and
a third semiconductor body that includes an active surface housing a first electrical-contact pad, said second semiconductor body housing a second electrical-contact pad, said third semiconductor body being electrically coupled to said second semiconductor body in a flip-chip configuration with the solder ball arranged between the first and the second electrical-contact pads.

9. The package according to claim 8 , wherein the second semiconductor body further includes a redistribution layer that extends over the first side of the second semiconductor body, said redistribution layer forming an electrical-connection path between the first electrical-contact region and said second electrical-contact pad of the second semiconductor body.

10. The package according to claim 8 , wherein said first semiconductor body has side surfaces that are covered by said first coating layer and in direct contact with said first coating layer.

11. A package comprising:
a first semiconductor body integrating a first microelectromechanical structure;
a second semiconductor body having a first side that includes:
an active region integrating an electronic circuit that is coupled to the first microelectromechanical structure; and
a first electrical-contact region operatively coupled to said electronic circuit;

a first coating layer of resin located over the first semiconductor body and the second semiconductor body and having a first surface;
a first conductive through via extending through the first coating layer and electrically coupled to the first electrical-contact region;
a second electrical-contact region located on the first surface of the first coating layer and electrically coupled to the first conductive through via;
bonding wire; and
a third semiconductor body that includes an active surface housing a first electrical-contact pad, wherein said second semiconductor body houses a second electrical-contact pad,
wherein said third semiconductor body is electrically coupled to said second semiconductor body by the bonding wire, wherein the bonding wire is coupled between the first and second electrical-contact pads.

12. The package according to claim 11 , wherein the second semiconductor body further includes a redistribution layer that extends over the first side of the second semiconductor body, said redistribution layer forming an electrical-connection path between the first electrical-contact region and said second electrical-contact pad of the second semiconductor body.

13. An electronic apparatus comprising:
a printed circuit; and
a package that includes:
a first semiconductor body integrating a first microelectromechanical structure;
a second semiconductor body having a first surface that includes:
an active region integrating an electronic circuit; and
a first electrical-contact region that is electrically co

Assignees

• St Microelectronics Srl
• Stmicroelectronics (Malta) Ltd

Inventors

• Formosa Kevin
• Maggi Luca

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title