Delta-sigma modulator having differential output

Patent metadata

Field	Value
Publication number	US-9444489-B2
Application number	US-201514805628-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	Nov 24, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Provided is a delta-sigma modulator having a differential output, the modulator including a switched-capacitor integrator configured to generate a non-inverted integral signal and an inverted integral signal and also including a switched-capacitor circuit configured to sample an input signal based on a control signal and to integrate the feedback signal and the input signal based on the control signal and also a feedback circuit configured to generate the feedback signal.

First claim

What is claimed is:

1. A switched-capacitor integrator comprising:
an amplifier comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a first integrating capacitor situated between the first input terminal and the first output terminal;
a second integrating capacitor situated between the second input terminal and the second output terminal; and
a switched-capacitor circuit configured to sample an input signal based on a control signal, and configured to integrate the input signal and a feedback signal using the first integrating capacitor and the second integrating capacitor based on the control signal.

2. The integrator of claim 1 , wherein the first output terminal is configured to provide a non-inverted output signal from the integration of the input signal, and the second output terminal is configured to provide an inverted output signal from the integration of the input signal.

3. The integrator of claim 1 , further comprising:
a feedback circuit configured to generate the feedback signal by sampling a reference signal using a feedback capacitor, and to transfer the feedback signal into the switched-capacitor circuit.

4. The integrator of claim 3 , wherein the reference signal comprises a non-inverted reference signal and an inverted reference signal, and the feedback circuit is configured to generate the feedback signal by sampling at least one of the non-inverted reference signal and the inverted reference signal based on the control signal.

5. The integrator of claim 3 , wherein the feedback circuit comprises:
a first feedback circuit configured to generate a first feedback signal based on the reference signal, and to transfer the first feedback signal into the first integrating capacitor; and
a second feedback circuit configured to generate a second feedback signal based on the reference signal, and to transfer the second feedback signal into the second integrating capacitor.

6. The integrator of claim 3 , wherein the control signal comprises a first control signal used to control the switched-capacitor circuit and a second control signal used to control the feedback circuit, and the second control signal is generated based on the first control signal.

7. The integrator of claim 6 , wherein the first control signal is generated based on an output signal of the first output terminal and an output signal of the second output terminal.

8. The integrator of claim 1 , wherein the switched-capacitor circuit comprises:
a first sampling capacitor configured to integrate the input signal using the first integrating capacitor;
a second sampling capacitor configured to integrate the input signal using the second integrating capacitor; and
an array of switches controlled based on a clock phase of the control signal.

9. The integrator of claim 8 , wherein the array of switches is controlled based on the clock phase such that the input signal is transmitted into at least one of the first sampling capacitor and the second sampling capacitor, and an output signal of the first sampling capacitor is integrated using the first integrating capacitor while the output signal of the first sampling capacitor is simultaneously integrated using the second integrating capacitor.

10. The integrator of claim 8 , wherein the clock phase comprises:
a first clock phase in which the input signal is sampled using the first sampling capacitor; and
a second clock phase in which an output signal of the first sampling capacitor and an output signal of a first feedback capacitor are integrated using the first integrating capacitor, and an output signal of the second sampling capacitor and an output signal of a second feedback capacitor are integrated using the second integrating capacitor.

11. A delta-sigma modulator comprising:
a digital-to-analog converter (DAC) configured to generate a feedback signal using a reference signal; and
a switched-capacitor integrator configured to sample an input signal based on a control signal and integrate the feedback signal and the input signal based on the control signal, thereby generating a non-inverted integral signal and an inverted integral signal.

12. The modulator of claim 11 , further comprising:
a comparator configured to generate an L-bit digital bitstream based on the non-inverted integral signal and the inverted integral signal, wherein L is a natural number.

13. The modulator of claim 11 , wherein the switched-capacitor integrator comprises:
an amplifier comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a first integrating capacitor situated between the first input terminal and the first output terminal;
a second integrating capacitor situated between the second input terminal and the second output terminal;
a switched-capacitor circuit configured to sample the input signal based on the control signal, and configured to integrate the input signal and the feedback signal using the first integrating capacitor and the second integrating capacitor based on the control signal; and
a feedback circuit configured to generate the feedback signal by sampling the reference signal using a feedback capacitor, and to transfer the feedback signal into the switched-capacitor circuit.

14. The modulator of claim 13 , wherein the feedback signal comprises a non-inverted feedback signal and an inverted feedback signal, and the feedback circuit is configured to transfer at least one of the non-inverted feedback signal and the inverted feedback signal to the switched-capacitor circuit based on the control signal.

15. The modulator of claim 13 , wherein the control signal comprises a first control signal used to control the switched-capacitor circuit and a second control signal used to control the feedback circuit, and the second control signal is generated based on the first control signal.

16. The modulator of claim 15 , wherein the first control signal is generated based on an output signal output from the first output terminal and an output signal of the second output terminal.

17. The modulator of claim 13 , wherein the switched-capacitor circuit comprises an array of switches controlled based on a clock phase of the control signal such that the input signal is transmitted into at least one of a first sampling capacitor and a second sampling capacitor, and an output signal of the first sampling capacitor is integrated using the first integrating capacitor while the output signal of the first sampling capacitor is simultaneously integrated using the second integrating capacitor.

18. An operation method of a switched-capacitor integrator, the method comprising:
sampling an input signal based on a clock phase of a control signal; and
generating a non-inverted integral signal and an inverted integral signal by differently integrating the input signal and a feedback signal using a same integrating capacitor in different integration intervals of the control signal.

19. An operation method of a delta-sigma modulator, the method comprising:
generating a feedback signal using a reference signal;
sampling an input signal based on a control signal; and
generating a non-inverted integral signal and an inverted integral signal by integrating the input signal and the feedback signal based on the control signal.

20. The method of claim 19 , wherein the sampling and generating are performed based on a clock phase of the control signal.

21. The method of cl

Assignees

• Samsung Electronics Co Ltd
• Industry-Univ Coop Found Hanyang Univ Erica Campus

Inventors

• Roh Jeongjin
• Kim Jong Pal
• Jung Youngjae
• Duan Quanzhen
• Lee Tak Hyung
• Choi Danbi

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• G06G7/184

  using capacitive elements · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M3/496 Primary

  Details of sampling arrangements or methods · CPC title