Multiple stage digital to analog converter

Patent metadata

Field	Value
Publication number	US-9444487-B1
Application number	US-201514838097-A
Country	US
Kind code	B1
Filing date	Aug 27, 2015
Priority date	Aug 27, 2015
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

First claim

The invention claimed is:

1. A multi-stage Digital to Analog Convertor (DAC) comprising:
a first stage comprising a first set of circuit components,
a second stage comprising a second set of circuit components and
a third stage comprising a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths;
wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in the first mode the first stage is switchably coupled to the second stage independently of the third stage; in the second mode, the load is coupled and presented to a first part of the second stage of circuit components and in the third mode the load is coupled and presented to a second, different, part of the second stage of circuit components.

2. The DAC of claim 1 wherein the load comprises a first variable resistor.

3. The DAC of claim 1 wherein the load comprises a digitally variable impedance element.

4. The DAC of claim 1 further comprising a multiplexer configured to selectively couple the load the second stage of circuit components.

5. The DAC of claim 4 wherein the multiplexer defines first and second switchable paths from the load to the second stage of circuit components.

6. The DAC of claim 4 wherein the third stage comprises a digital rheostat, the multiplexer being a component of the digital rheostat.

7. The DAC of claim 4 wherein the third stage comprises a first multiplexer and a second multiplexer, operable selection of either the first multiplexer or the second multiplexer providing the first and second individual switchable impedance paths.

8. The DAC of claim 1 further comprising a set of switches arranged in series with the load to selectively couple the load to the second stage.

9. The DAC of claim 1 wherein the third stage comprises a first load and a second load, each of the first load and second load being presented independently of the other of the second and first load to the second stage of circuit components.

10. The DAC of claim 9 wherein each of the first load and the second load comprises a variable resistor.

11. The DAC of claim 10 wherein resistances of each of the first and second variable resistors have overlapping impedance ranges.

12. The DAC of claim 9 wherein at least one of the first load and the second load comprises a digitally variable impedance element.

13. The DAC of claim 12 wherein each of the first load and the second load comprises a digitally variable impedance element.

14. The DAC of claim 1 wherein the load is provided by a resistor network comprising a plurality of resistors that are individually switchable to define both Most Significant Bit, MSB, and Least Significant Bit, LSB transitions within the DAC.

15. The DAC of claim 1 wherein the third stage is configured to provide each of a high resolution path and a low resolution path from the first stage to an output of the DAC.

16. The DAC of claim 1 wherein the third stage comprises a programmable resistance network providing a plurality of individual switchable impedance paths.

17. The DAC of claim 16 wherein the programmable resistance network is configured to be digitally controlled.

18. The DAC of claim 1 wherein the DAC is configured to activate each of the modes of operation in a leap frog arrangement such that for each impedance element in the first stage a switching regime is effected to activate the first, second and third modes.

19. The DAC of claim 18 configured such that on transition from coupling a first impedance element of the first stage to the second stage to sequentially coupling a second impedance element in the first stage to the second stage that the existing mode is maintained.

20. A method of converting a digital input code to an analog equivalent, the method comprising
Providing a multi-stage Digital to Analog Convertor, DAC, comprising a first stage comprising a first set of circuit components, a second stage comprising a second set of circuit components and a third stage comprising a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths;
Operating the DAC in each of a distinct first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components.

21. The method of claim 20 further comprising analysing the digital input code and in response to the analysis of the digital input code selecting one of the first mode, second mode, and third mode.

22. The method of claim 21 wherein the analysing the digital input code comprises determining transitions from each of the first mode, the second mode and the third mode to others of the first mode, second mode and third mode.

23. The method of claim 22 wherein the first stage comprises a plurality of impedance elements provided in a string arrangement and the determining transitions comprises effecting a leapfrog switching regime.

24. The method of claim 22 wherein the determining the transitions from each of the first mode, the second mode and the third mode to others of the first mode, second mode and third mode is ascertained from a digitally encoded DAC transfer function.

25. The method of claim 20 comprising providing a set of switches and using the set of switches to effect a switching of the load within the third stage and concurrently also to effect a switching of individual impedance elements within the second stage.

26. A digital to analog converter circuit, comprising:
a first stage comprising a first set of circuitry means, a second stage comprising a second set of circuitry means and a third stage comprising a third set of circuitry means, the third stage providing a load within first and second individual switchable impedance means;
means for operating the DAC in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is coupled via switchable coupling means to the second stage independently of the third stage; in a second mode, the load is coupled via coupling means and presented to a first part of the second stage of circuitry means, and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuitry means.

Assignees

• Analog Devices Global

Inventors

• Dempsey Dennis A

Classifications

• H03M1/785 Primary

  using resistors, i.e. R-2R ladders · CPC title

• H03M1/682 Primary

  both converters being of the unary decoded type · CPC title

• H03M1/765

  using a single level of switches which are controlled by unary decoded digital signals · CPC title