Oscillator with frequency control
US-2024250667-A1 · Jul 25, 2024 · US
Switch circuit
US9444451B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9444451-B2 |
| Application number | US-201414469207-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 26, 2014 |
| Priority date | Feb 29, 2012 |
| Publication date | Sep 13, 2016 |
| Grant date | Sep 13, 2016 |
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Abstract
Official abstract text for this publication.
Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled.
First claim
Opening claim text (preview).
What is claimed is: 1. A switch circuit for routing one of a positive voltage and a negative voltage from and input terminal to an output terminal, the switch circuit comprising: a first NMOS transistor including a drain connected to the input terminal, a source connected to a first node, and a gate connected to a control terminal; a second NMOS transistor including a drain connected to the first node, a source connected to a second node, and a gate connected to the control term…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H03K17/687Primary
Electricity · mapped topic
Electricity · mapped topic
- H03K17/063Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9444451B2 cover?
- Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmissio…
- Who is the assignee on this patent?
- Seiko Instr Inc, Sii Semiconductor Corp
- What technology area does this patent fall under?
- Primary CPC classification H03K17/687. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).