Boost PFC converter, method and control circuit used for boost PFC converter

Patent metadata

Field	Value
Publication number	US-9444327-B2
Application number	US-201414575835-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 20, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A boost PFC converter, a method and a control circuit used for boost PFC converter are discussed in the present invention. The boost PFC converter decreases the switching frequency when a line voltage is around zero, so that the whole operating efficiency is not decreased.

First claim

I claim:

1. A control circuit used in a boost PFC converter, the boost PFC converter is configured to receive an input signal to provide an output signal, the boost PFC converter includes a rectifier, an energy storage component, a first power switch, a second power switch and a zero crossing detector generating a zero crossing detecting signal indicative of a zero crossing condition of a current flowing through the energy storage component, the control circuit comprising:
a peak holding circuit, configured to receive a current sense signal indicative of the current flowing through the energy storage component, and to generate a peak holding signal indicative of the peak current flowing through the energy storage component;
a saw-tooth wave generator, configured to generate a saw-tooth wave signal;
a first comparator, configured to receive the peak holding signal, the saw-tooth wave signal, and a reference voltage, to generate a comparison signal by comparing the sum of the peak holding signal and the saw-tooth wave signal with the reference voltage;
a logical unit, having a first input terminal coupled to the first comparator to receive the comparison signal, a second input terminal configured to receive the zero crossing detecting signal, and an output terminal configured to generate a dead time signal;
a logical NOR circuit, having a first input terminal coupled to the output terminal of the logical unit to receive the dead time signal, a second input terminal configured to receive the zero crossing detecting signal, and an output terminal configured to generate the set signal;
a voltage converting unit, configured to receive a fixed voltage and the dead time signal, to generate a converting voltage;
a voltage-current converter, coupled to the voltage converting unit to receive the converting voltage, and to generate a current signal proportional to the converting voltage;
a first charge capacitor and a charge switch, parallel coupled between the voltage-current converter and the reference ground, wherein the charge switch 94 has an opposite switching status to the first power switch;
an error amplifier, having a first input terminal configured to receive a feedback signal indicative of the output signal, a second input terminal configured to receive a voltage reference signal, and an output terminal configured to generate a compensation signal by amplifying and integrating the difference between the feedback signal and the voltage reference signal;
a second comparator, having a first input terminal configured to receive a voltage across the first charge capacitor, a second input terminal coupled to the output terminal of the error amplifier to receive the compensation signal, and an output terminal configured to generate the reset signal by comparing the voltage across the first charge capacitor with the compensation signal; and
a logical circuit, having a set input terminal coupled to the logical NOR circuit to receive the set signal, a reset input terminal coupled to the output terminal of the second comparator to receive the reset signal, and an output terminal configured to generate a switch control signal to control the first power switch.

2. The control circuit of claim 1 , wherein the peak holding circuit comprises:
an operational amplifier, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the current sense signal;
a diode, having an anode and a cathode, wherein the anode is coupled to the output terminal of the operational amplifier, the cathode is coupled to the second input terminal of the operational amplifier;
a sample hold resistor, coupled between the cathode of the diode and the reference ground;
a sample hold capacitor, coupled between the cathode of the diode and the reference ground; wherein a voltage across the sample hold capacitor is the peak holding signal.

3. The control circuit of claim 1 , wherein the saw-tooth wave generator is configured to receive the dead time signal, to start to increase in response to a rising edge of the dead time signal and to fall quickly in response to a falling edge of the dead time signal.

4. The control circuit of claim 1 , wherein at the voltage converting unit, the converting voltage, the dead time signal and the fixed voltage has a following relationship:

V
DT

=

V
R

×

(

T
-

t
H

)

T

wherein VDT represents a voltage level of the converting voltage, VR represents a voltage level of the fixed voltage, T represents a switching cycle of the dead time signal, and tH represents the duration of the dead time signal in a switching cycle.

5. The control circuit of claim 1 , wherein at the logical unit, the dead time signal turns to logical high in response to a falling edge of the zero crossing detecting signal, and turns to logical low in response to a falling edge of the comparison signal.

6. The control circuit of claim 1 , further comprising: a short pulse circuit, coupled between the output terminal of the logical NOR circuit and the set input terminal of the logical circuit, wherein the he short pulse circuit is configured to receive the set signal, to generate a short pulse signal to the set input terminal S of the logical circuit.

7. The control circuit of claim 1 , further comprising: an operation unit, configured to receive the peak holding signal and the saw-tooth wave signal, to execute add operation on the peak holding signal and the saw-tooth wave signal, and to provide the operation result to the first comparator.

8. A boost PFC converter, comprising:
a first input port and a second input port, configured to receive an AC input signal;
an output port, configured to provide an output signal;
a rectifier, coupled to the first input port and the second input port to receive the AC input signal and to generate a rectified signal;
an energy storage component having a first terminal and a second terminal, the first terminal being configured to receive the rectified signal;
a first power switch, coupled between the second terminal of the energy storage component and a reference ground, the first power switch having a control terminal configured to receive a switch control signal;
a second power switch, coupled between the second terminal of the energy storage component and the output port;
a zero crossing detector, configured to generate a zero crossing detecting signal indicative of a zero crossing condition of a current flowing through the energy storage component;
a peak holding circuit, configured to receive a current sense signal indicative of the current flowing through the energy storage component, and to generate a peak holding signal indicative of the peak current flowing through the energy storage component;
a saw-tooth wave generator, configured to generate a saw-tooth wave signal;
a first comparator, configured to receive the peak holding signal, the saw-tooth wave signal, and a reference voltage, to generate a comparison signal by comparing the sum of the peak holding signal and the saw-tooth wave signal with the reference voltage;
a logical unit, havin

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Lin Sicong

Classifications

• H02M1/4241 Primary

  using a resonant converter · CPC title

• H02M1/4225 Primary

  using a non-isolated boost converter · CPC title

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• H02M2001/0054

  Electricity · mapped topic

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title