Pin arrangement and electronic assembly

US9444165B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9444165-B2
Application numberUS-201414551094-A
CountryUS
Kind codeB2
Filing dateNov 24, 2014
Priority dateSep 16, 2014
Publication dateSep 13, 2016
Grant dateSep 13, 2016

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

First claim

Opening claim text (preview).

What is claimed is: 1. A pin arrangement, adapted to a flexible printed circuit connector, the pin arrangement comprising: a pin lane, comprising: a pair of ground pins; a pair of differential pins, located between the pair of ground pins; at least one middle not-connected pin, located between the pair of differential pins; and a pair of side not-connected pins, wherein each of the pair of the side not-connected pins is located between one of the pair of ground pins and one of the pair of differential pins adjacent thereto and is not located between the pair of differential pins. 2. The pin arrangement as claimed in claim 1 , wherein the at least one middle not-connected pin is a floating pin. 3. The pin arrangement as claimed in claim 1 , wherein the pair of side not-connected pins are floating pins. 4. The pin arrangement as claimed in claim 1 , wherein the pair of differential pins is adopt to USB, SATA, HDMI, PCIE or DP. 5. The pin arrangement as claimed in claim 1 , further comprising: another pin lane, comprising: another pair of ground pins; and another pair of differential pins, located between the another pair of ground pins. 6. The pin arrangement as claimed in claim 5 , wherein the another pin lane further comprises: another at least one middle not-connected pin, located between the another pair of differential pins. 7. The pin arrangement as claimed in claim 5 , wherein the another pin lane further comprises: another pair of side not-connected pins, wherein each of the another pair of the side not-connected pins is located between one of the another pair of ground pins and one of the another pair of differential pins adjacent thereto, and is not located between the another pair of differential pins. 8. An electronic assembly, comprising: two printed circuit boards; two flexible printed circuit connectors, respectively mounted on the printed circuit boards; and a flexible printed circuit, having two contact portions respectively connected to the flexible printed circuit connectors, so as to electrically connect the flexible printed circuit connectors, wherein each of the flexible printed circuit connectors has a pin arrangement, and the pin arrangement comprises: a pin lane, comprising: a pair of ground pins; a pair of differential pins, located between the pair of ground pins; at least one middle not-connected pin, located between the pair of differential pins; and a pair of side not-connected pins, wherein each of the pair of the side not-connected pins is located between one of the pair of ground pins and one of the pair of differential pins adjacent thereto and is not located between the pair of differential pins. 9. The electronic assembly as claimed in claim 8 , wherein the flexible printed circuit has a plurality of flexible printed circuit traces and a plurality of flexible printed circuit pads, and the flexible printed circuit pads respectively contacting the at least one middle not-connected pins are not connected to each other through the flexible printed circuit traces. 10. The electronic assembly as claimed in claim 8 , wherein the printed circuit board has a plurality of printed circuit board pads and a plurality of printed circuit board traces, and the printed circuit board pad connecting to the at least one middle not-connected pin is not connected to the printed circuit board traces. 11. The electronic assembly as claimed in claim 8 , wherein the flexible printed circuit has a plurality of flexible printed circuit traces and a plurality of flexible printed circuit pads, and the flexible printed circuit pads respectively contacting the side not-connected pins are not connected to each other through the flexible printed circuit traces. 12. The electronic assembly as claimed in claim 8 , wherein the printed circuit board has a plurality of printed circuit board pads and a plurality of printed circuit board traces, and the printed circuit board pad connecting to the side not-connected pin is not connected to the printed circuit board traces. 13. The electronic assembly as claimed in claim 8 , further comprising: another pin lane, comprising: another pair of ground pins; and another pair of differential pins, located between the another pair of ground pins. 14. The electronic assembly as claimed in claim 13 , wherein the another pin lane further comprises: another at least one middle not-connected pin, located between the another pair of differential pins. 15. The electronic assembly as claimed in claim 13 , wherein the another pin lane further comprises: another pair of side not-connected pins, wherein each of the another pair of the side not-connected pins is located between one of the another pair of ground pins and one of the another pair of differential pins adjacent thereto and is not located between the another pair of differential pins. 16. A pin arrangement, adapted to a flexible printed circuit connector, the pin arrangement comprising: a pin lane, comprising: a pair of ground pins; a pair of differential pins, located between the pair of ground pins; and at least one not-connected pin, located between one of the pair of ground pins and one of the pair of differential pins adjacent thereto, and not located between the pair of differential pins. 17. The pin arrangement as claimed in claim 16 , wherein the at least one not-connected pin is a floating pin. 18. The pin arrangement as claimed in claim 16 , wherein the pair of differential pins is adopt to USB, SATA, HDMI, PCIE or DP.

Assignees

Inventors

Classifications

  • Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components · CPC title

  • Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

  • Impedance matching · CPC title

  • specially for flexible printed circuits, e.g. using folded portions · CPC title

  • by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] · CPC title

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What does patent US9444165B2 cover?
A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins an…
Who is the assignee on this patent?
Via Tech Inc
What technology area does this patent fall under?
Primary CPC classification H05K1/025. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).