Piezoelectronic transistor with co-planar common and gate electrodes

US9444029B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9444029-B2
Application numberUS-201514747137-A
CountryUS
Kind codeB2
Filing dateJun 23, 2015
Priority dateOct 31, 2014
Publication dateSep 13, 2016
Grant dateSep 13, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.

First claim

Opening claim text (preview).

What is claimed is: 1. A piezoelectronic transistor (PET), comprising: a piezoelectric (PE) element with a trench formed therein; a pair of electrodes disposed on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element; a piezoresistive (PR) element above the pair of electrodes; and a clamp above the PR element, wherein the PE element is configured to be displaced perpendicular to the first plane, based on a voltage applied to the pair of electrodes. 2. The PET according to claim 1 , wherein a width of the trench is defined by a distance between the pair of electrodes. 3. The PET according to claim 1 , wherein the PE element is comprised of lead magnesium niobate-lead titanate (PMN-PT) and an increase in a depth of the trench increases a displacement of the PE element and a resulting pressure on the PR element when the voltage is applied to the pair of electrodes and an electric field is generated in the PE element. 4. The PET according to claim 1 , wherein the PE element is comprised of lead zirconate titanate (PZT) and a decrease in the thickness of the PR element increases a pressure on the PR element when the voltage is applied to the pair of electrodes. 5. The PET according to claim 1 , wherein an increase in an angle of the trench increases a displacement of the PE element and a resulting pressure on the PR element when the voltage is applied to the pair of electrodes and an electric field is generated in the PE element. 6. The PET according to claim 1 , further comprising a dielectric anchor to secure the clamp and prevent movement of the clamp based on a displacement of the PE element. 7. The PET according to claim 1 , wherein the claim is a stand-alone configured to be anchored by a side gate of the PET. 8. A semiconductor device, comprising: a piezoelectronic transistor (PET) comprising a piezoelectric (PE) element with a trench formed therein, a pair of electrodes disposed on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element, and a piezoresistive (PR) element above the pair of electrodes; and a voltage source configured to apply a voltage to the pair of electrodes, the voltage resulting in an electric field in the PE element, wherein the PE element is configured to be displaced in a second plane, perpendicular to the first plane, based on the electric field in the PE element. 9. The device according to claim 8 , further comprising a clamp of the PET above the PR element. 10. The device according to claim 8 , wherein the PE element is comprised of lead magnesium niobate-lead titanate (PMN-PT) and an increase in a depth of the trench increases a displacement of the PE element and a resulting pressure on the PR element when the voltage is applied to the pair of electrodes and the electric field is generated in the PE element. 11. The device according to claim 8 , wherein the PE element is comprised of lead zirconate titanate (PZT) and an decrease in a width of the PR element increases a pressure on the PR element when the voltage is applied to the pair of electrodes. 12. The device according to claim 8 , wherein an increase in an angle of the trench increases a displacement of the PE element and a resulting pressure on the PR element when the voltage is applied to the pair of electrodes and the electric field is generated in the PE element.

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What does patent US9444029B2 cover?
A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L41/0805. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).