Manufacturing method of semiconductor film, manufacturing method of semiconductor device, and manufacturing method of photoelectric conversion device

Patent metadata

Field	Value
Publication number	US-9443989-B2
Application number	US-201113172359-A
Country	US
Kind code	B2
Filing date	Jun 29, 2011
Priority date	Jul 2, 2010
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, comprising the steps of:
forming a gate electrode over a substrate;
forming a gate insulating film over the substrate and the gate electrode;
forming a microcrystalline semiconductor film over the gate insulating film;
forming a semiconductor film comprising a microcrystalline semiconductor region and an amorphous semiconductor region, over the microcrystalline semiconductor film;
forming an amorphous semiconductor film containing an impurity element, over the semiconductor film by a method comprising:
introducing a mixture of a deposition gas containing silicon and a gas containing an impurity element as a source gas into a reaction chamber;
setting pressure and an electrode distance in the reaction chamber so that a discharge inception voltage is a minimum discharge inception voltage in a Paschen curve; and
applying a pulse-modulated discharge inception voltage to electrodes, wherein the pulse-modulated discharge inception voltage is obtained by pulse-modulating the discharge inception voltage, wherein the discharge inception voltage is pulse-modulated at a frequency higher than or equal to 1 kHz and lower than or equal to 12.5 kHz;

forming an island-shaped amorphous semiconductor film containing the impurity element and an island-shaped first semiconductor stack, the island-shaped amorphous semiconductor film being formed by etching part of the amorphous semiconductor film, and the island-shaped first semiconductor stack being formed by etching parts of the microcrystalline semiconductor film and the semiconductor film;
forming wirings functioning as a source electrode and a drain electrode, over the island-shaped amorphous semiconductor film; and
forming a pair of amorphous semiconductor films containing the impurity element functioning as a source region and a drain region by etching the island-shaped amorphous semiconductor film;
the method manufacturing method, further comprising the steps of:
forming a second semiconductor stack in which a microcrystalline semiconductor region and a pair of amorphous semiconductor regions are stacked, by etching part of the island-shaped first semiconductor stack;
forming an insulating film over the wirings, the pair of amorphous semiconductor films containing the impurity element, the second semiconductor stack, and the gate insulating film; and
forming a back-gate electrode over the insulating film.

2. The manufacturing method according to claim 1 , further comprising the step of exposing a side surface of the island-shaped first semiconductor stack to plasma before forming the wirings, so that a barrier region is formed on the side surface of the island-shaped first semiconductor stack.

3. The manufacturing method according to claim 1 , wherein the gate electrode and the back-gate electrode are parallel to each other.

4. The manufacturing method according to claim 1 , wherein the gate electrode and the back-gate electrode are connected to each other.

5. The manufacturing method according to claim 1 , wherein the back-gate electrode is in a floating state.

6. The manufacturing method according to claim 1 , wherein the source gas further comprises hydrogen.

Assignees

• Tanaka Tetsuhiro
• Kato Erika
• Semiconductor Energy Lab

Inventors

• Tanaka Tetsuhiro
• Kato Erika

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24 Primary

  using chemical vapour deposition [CVD] · CPC title

• Y02E10/544

  Solar cells from Group III-V materials · CPC title